DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 4, 8 and 10 – 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Islam et al. (US 2022/0130996).
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(Claim 1) Islam et al. teach a power semiconductor device comprising:
a semiconductor layer including silicon carbide (SiC, paragraph 110);
a trench in the semiconductor layer (260, paragraph 111);
a gate (264) having a first region buried in the trench and a second region extending over the semiconductor layer (T-shaped);
a shield region (SHIELD) surrounding a lower region of the trench;
a well region (232, WELL) disposed in the semiconductor layer to be in contact with a first side (left side) surface of the trench and an upper surface of the semiconductor layer;
a source region (S) disposed in the well region (WELL); and
a shield connector (272) extending from the upper surface of the semiconductor layer to the shield region while contacting a second side (right side) surface opposite to the first side surface of the trench.
(Claim 2) Islam et al. teach wherein the first region (leg of T-shaped) includes a recess gate buried in the trench and configured to form a vertical channel in the well region when operation power is received; and
the second region (bar of T-shaped) includes a planar gate disposed over the semiconductor layer to be connected to the recess gate and configured to form a horizontal channel in the well region when the operation power is received.
(Claim 3) Islam et al. teach wherein the planar gate (bar of T-shaped) extends to cover the well region (WELL) while connected to a partial region adjacent to the source region (S) from an upper surface of the recess gate.
(Claim 4) Islam et al. teach wherein the shield region (SHIELD) is disposed in a manner such that the shield region protrudes from opposing sides of the trench in opposing directions, and both sides of the shield region are symmetrical with respect to the trench.
(Claim 8) Islam et al. teach wherein the semiconductor layer includes a silicon carbide (SiC) substrate, and a silicon carbide (SiC) epitaxial layer (paragraph 110).
(Claim 10) Islam et al. teach the power semiconductor device, further comprising:
a drain electrode (282) disposed under the semiconductor layer; and
a source electrode (280) disposed over the gate and the semiconductor layer to be connected to the shield connector (272).
(Claim 11) Islam et al. teach a method for manufacturing a power semiconductor device comprising:
forming a shield region (fig. 1B #70, paragraph 86) by implanting impurities of a second conductivity type (P) opposite to a first conductivity type (N) into a semiconductor layer including silicon carbide (SiC) having the first conductivity type;
forming a trench extending to an upper region of the shield region by etching the semiconductor layer (fig. 1B #60);
forming a shield connector (fig. 1C #72) connecting the shield region to an upper surface of the semiconductor layer by implanting impurities of the second conductivity type into one side of the trench;
forming a well region (fig. 1C #32 right) spaced apart from the shield region (70) by implanting the impurities of the second conductivity type (P) into another side opposite to the one side of the trench;
forming a source region (42, paragraph 86) by implanting impurities of the first conductivity type into the well region; and
forming a gate (fig. 1D #GATE) in a manner such that a partial region of the gate is buried in the trench and another partial region of the gate extends over the semiconductor layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7, 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Islam et al. (US 2022/0130996) in view of Meiser et al. (US 2019/0296110).
(Claim 7) Islam et al. lack the power semiconductor device, further comprising: a junction field effect transistor (JFET) region disposed between the well region and the shield region in the semiconductor layer.
However, Meiser et al. teach the power semiconductor device, further comprising a junction field effect transistor (JFET) region (fig. 6B #1311, paragraph 116) disposed between the well region (fig. 7A #120) and the shield region (fig. 7B #160) in the semiconductor layer for the benefit of effectively protecting the trench gate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of effectively protecting the trench gate.
(Claim 9) Islam et al. lack wherein the silicon carbide (SiC) epitaxial layer includes a field stopper, and a drift region disposed over the field stopper.
However, Meiser et al. teach wherein the silicon carbide (SiC) epitaxial layer (paragraph 132) includes a field stopper, and a drift region disposed over the field stopper (paragraph 133) for the benefit of confining carriers, and preventing premature breakdown.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of confining carriers, and preventing premature breakdown.
(Claim 13) Islam et al. lack wherein the forming of the trench includes etching the semiconductor layer to a position where a lower region of the trench is surrounded by the shield region.
However, Meiser et al. teach wherein the forming of the trench includes etching the semiconductor layer to a position where a lower region of the trench (fig. 15 #750) is surrounded by the shield region (160) for the benefit of forming rounded corners in the shield region thereby reducing electric field concentration (fig. 16B #750).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of forming rounded corners in the shield region with reduced electric field concentration.
Allowable Subject Matter
Claims 5 – 6, 12 and 14 – 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
Contact Information
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
December 9, 2025