Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Effective Priority Date of Application
Claims benefit of Provisional application, 63/425,094 filed 11-14-2022.
Response to Amendment
Claims 1-20 are currently pending.
The amendment filed on 12-16-2026 has been entered.
The 112(d) rejection has been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Although claims 1-6, 8-13, and 15-20 were previously indicated as allowed and claims 7 and 14 were objected to as allowable if rewritten in independent form to include all intervening claims features, upon an updated search and consideration, the allowable subject matter is withdrawn in view of new cited prior art.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 8, and 15 recites the limitation "the counter value." There is insufficient antecedent basis for this limitation in the claim.
Claims 1, 8, and 15 recites the limitation "a threshold criterion," a second time. There is insufficient antecedent basis for this limitation in the claim.
Claims 7 and 14 recites the limitation "the value." There is insufficient antecedent basis for this limitation in the claim. It likely should state “the counter value.”
Claims 13, 16, and 19 recites the limitation "a threshold criterion," a second time. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-6, 9-12, 17-18, and 20 are rejected for incorporating the indefiniteness of their respective base claims and intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Muchherela et al., WO 2019/045943 A1, published on 03/07/2019, and filed on 08/01/2018, hereinafter “Muchherela”.
As to claims 1 and 8, Muchhela discloses:
(Previously presented) A system comprising:
a memory device (642); and
a processing device, operatively coupled to the memory device (110, 642), to perform operations comprising: See [0024];
receiving, from a host system (105, 641), a memory access command; See [0025]; [0028];
responsive to determining that the memory access command is a program command (read, write, erase), incrementing a counter of a number of consecutive program commands received by the memory device, wherein receiving a threshold number of read commands or erase commands resets the counter; See Fig. 7; [0076-0077];
determining whether the counter value satisfies a threshold criterion; See [0076-0077]; and
responsive to determining that the counter value satisfies a threshold criterion, setting an initial polling timer (749) to a value associated with the counter value satisfying the threshold criterion; See Fig. 7; [0074-0077].
[0024] Electronic devices can be broken down into several main components: a processor (e.g., a central processing unit (CPU) or other main processor); memory (e.g., one or more volatile or non-volatile random-access memory (RAM) memory device, such as dynamic RAM (DRAM), mobile or low-power double-data-rate synchronous DRAM (DDR SDRAM), etc.); and a storage device (e.g., non-volatile memory (NVM) device, such as flash memory, read-only memory (ROM), an SSD, an MMC, or other memory card structure or assembly, etc.). In certain examples, electronic devices can include a user interface (e.g., a display, touchscreen, keyboard, one or more buttons, etc.), a graphics processing unit (GPU), a power management circuit, a baseband processor or one or more transceiver circuits, etc.
[0025] Figure 1 illustrates an example of an environment 100 including a host device 105 and a memory device 110 configured to communicate over a communication interface. The host device 105 or the memory device 110 may be included in a variety of products 150, such as Internet of Things (IoT) devices (e.g., a refrigerator or other appliance, sensor, motor or actuator, mobile communication device, automobile, drone, etc.) to support processing, communications, or control of the product 150.
[0074] The time from the reference time, for instance time zero, can be monitored and compared to a selected time interval. The selected time interval can be the time between scheduled read level calibrations of NAND 742. The time between schedules real level calibrations can be referred to as tscan. Tscan can be set based on a user usage model. Tscan can be set in calibration controller 644 and can be changed with implementation or modification of a user usage model of NAND 742. At 759, a determination can be made as to whether the current monitored time is greater than tscan. If the current monitored time is not greater than tscan, this status need not be provided to calibration controller 744 and time tracker 749 continues to track the time from the reference time, if the current monitored time is greater than tscan, this status can be provided to calibration controller 744, and calibration controller 744 can trigger a read level calibration of NAND 742. Upon triggering the read level calibration or on completion of the read level calibration, calibration controller 744 can reset the time tracker, which can be a timer, to reference zero from which time tracker 749 continues to monitor time. In addition to setting time tracker 749 to reference zero, calibration controller 744 can reset NAND read counter 746 to a reference count, which can be a zero count, and reset NAND erase, write counter 748 to another reference count, which also can be a zero count. In an embodiment, with the monitored time of time tracker 749 equal to tscan, calibration controller 744 can operate in the same manner as for the monitored time being greater than tscan. In an alternative embodiment, with the monitored time of time tracker 749 equal to tscan, calibration controller 744 can operate in the same manner as for the monitored time being less than tscan.
[0075] Signals from NAND 742 that indicate completion of write operations and/or erase operations can be monitored to count write operations and/or erase operations by NAND erase, write counter 748. The number of erases counted and the number of writes counted can have different granularity. The number of erases can typically be the average erase count of NAND 742. The number of writes can typically be the number of pages written to NAND 742. At 758, a determination can be made as to whether the number of erases counted and/or the number of writes counted is greater than a predetermined threshold for erases and/or writes. If the current count of erases and/or writes is not greater than the predetermined threshold for erases and/or writes, this status need not be provided to calibration controller 744 and NAND erase, write counter 748 continues to track the number of erases and/or the number or writes. If the current count of erases and/or writes is greater than the predetermined threshold for erases and/or writes, this status can be provided to calibration controller 744, and calibration controller 744 can trigger a read level calibration of NAND 742.
[0076] Upon triggering the read level calibration or on completion of the read level calibration, calibration controller 744 can reset NAND erase, write counter 748 to its reference count, which also can be a zero count, from which NAND erase, write counter 748 again starts to count the number of erases and/or the number or writes by NAND 742. In addition to setting NAND erase, write counter 748 to reference count zero, calibration controller 744 can reset time tracker 749 to reference zero and reset NAND read counter to a reference count zero. If the count of NAND erase, write counter 748 does not reach the predetermined threshold for the number of erases and/or the number or writes by NAND 742 by tscan, then the event of the monitored time by time tracker 749 exceeding tscan will result in the NAND erase, write counter 748 being reset to reference zero. With NAND erase, write counter 748 working in conjunction with time tracker 749, the highest count of the NAND erase, write counter 748 occurs within the selected time, tscan. NAND erase, write counter 748 may be arranged as two counters with two predetermined thresholds. In an embodiment, with the monitored count of NAND erase, write counter 748 equal to the predetermined threshold, calibration controller 744 can operate in the same manner as for the count being greater than the threshold. In an alternative embodiment, with the monitored count of NAND erase, write counter 748 equal to its respective predetermined threshold, calibration controller 744 can operate in the manner as for the monitored time being less than the threshold.
[0077] Read operations from logic controller 747 to NAND 742 for reading form NAND 742 can be monitored to count read operations by NAND read counter 746. At 768, a determination can be made as to whether the number of read operations counted is greater than a predetermined threshold for read operations for NAND 742. If the current count of reads is not greater than the predetermined threshold for reads from NAND 742, this status need not be provided to calibration controller 744 and NAND read counter 746 continues to track the number of reads. If the current count of reads is greater than the predetermined threshold for reads, this status can be provided to calibration controller 744, and calibration controller 744 can trigger a read level calibration of NAND 742. [0078] Upon triggering the read level calibration or on completion of the read level calibration, calibration controller 744 can reset NAND read counter 746 to its reference count, which also can be a zero count, from which NAND read counter 746 again starts to count the number of reads to NAND 742. In addition to setting NAND read counter 746 to reference count zero, calibration controller 744 can reset time tracker 749 to reference zero and reset NAND erase, write counter 748 to a reference count zero. If the count of NAND read counter 746 does not reach the predetermined threshold for the number of reads by NAND 742 by tscan, then the event of the monitored time by time tracker 749 exceeding tscan will result in the NAND read counter 746 resetting to reference zero. With NAND read counter 748 working in conjunction with time tracker 749, the highest count of the NAND read counter 748 occurs within the selected time, tscan. In an embodiment, with the monitored count of NAND read counter 746 equal to its respective predetermined threshold, calibration controller 744 can operate in the same manner as for the count being greater than the predetermined threshold. In an alternative embodiment, with the monitored count of NAND read counter 746 equal to its respective predetermined threshold, calibration controller 744 can operate in the manner as for the monitored time being less than the threshold.
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As to claim 2, Muchhela discloses:
(Previously presented) The system of claim 1, wherein the operations further comprise:
responsive to determining that the counter value fails to satisfy the threshold criterion, setting the initial polling timer to a value associated with the counter value failing to satisfy the threshold criterion; “Failing to satisfy is deemed to be above the threshold”; See Fig. 7; [0074-0075].
As to claim 3, Muchhela discloses:
(Previously presented) The system of claim 2, wherein the value associated with the counter value failing to satisfy the threshold criterion is greater than the value associated the counter value satisfying the threshold criterion; “Failing to satisfy is deemed to be above the threshold”; See Fig. 7; [0075].
As to claim 4, Muchhela discloses:
(Previously presented) The system of claim 1, wherein the operations further comprise:
responsive to determining that the memory access command is a read command, resetting the counter value; See Fig. 7; [0075]; [0076].
As to claim 5, Muchhela discloses:
(Original) The system of claim 1, wherein the operations further comprise: responsive to determining that the memory access command is a read command, incrementing a read counter value; See Fig. 7; [0075]; [0076].
As to claim 6, Muchhela discloses:
(Previously presented) The system of claim 5, wherein the operations further comprise:
responsive to determining that the read counter value satisfies a threshold criterion, resetting the counter value; See Fig. 7; [0075]; [0076].
As to claim 7, Muchhela discloses:
(Currently Amended) The system of claim 1, wherein the operations further comprise:
issuing, to the memory device, the program command with the initial polling timer set to the value associated the counter value satisfying the threshold criterion; See Fig. 7; [0074-0076].
As to claim 9, Muchhela discloses:
(Previously presented) The method of claim 8, further comprising
responsive to determining that the counter value fails to satisfy the threshold criterion, setting the initial polling timer to a value associated with the counter value failing to satisfy the threshold criterion; See Fig. 7; [0074-0076].
As to claim 10, Muchhela discloses:
(Previously presented) The method of claim 9, wherein the value associated with the counter value failing to satisfy the threshold criterion is greater than the value associated the counter value satisfying the threshold criterion; See Fig. 7; [0074-0076].
As to claim 11, Muchhela discloses:
(Previously presented) The method of claim 8, further comprising:
responsive to determining that the memory access command is a read command, resetting the counter value; See Fig. 7; [0074-0076].
As to claim 12, Muchhela discloses:
(Original) The method of claim 8, further comprising:
responsive to determining that the memory access command is a read command, incrementing a read counter value; See Fig. 7; [0074-0076].
As to claim 13, Muchhela discloses:
(Previously presented) The method of claim 12, further comprising:
responsive to determining that the read counter value satisfies a threshold criterion, resetting the counter value; See Fig. 7; [0074-0076].
As to claim 14, Muchhela discloses:
(Currently Amended) The method of claim 8, further comprising:
issuing, to a memory device, the program command with the initial polling timer set to the value; See Fig. 7; [0074-0076].
As to claims 15-20, they are similarly rejected as stated above for their corresponding limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES RONES whose telephone number is (571)272-4085. The examiner can normally be reached M-F 9-5:30pm.
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CHARLES . RONES
Supervisory Patent Examiner
Art Unit 2136
/CHARLES RONES/Supervisory Patent Examiner, Art Unit 2168