Prosecution Insights
Last updated: April 19, 2026
Application No. 18/382,800

POWER AMPLIFIER CALIBRATION SYSTEM AND METHOD

Non-Final OA §103
Filed
Oct 23, 2023
Examiner
NGUYEN, HIEU P
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qorvo US Inc.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
1123 granted / 1220 resolved
+24.0% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
25 currently pending
Career history
1245
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
54.9%
+14.9% vs TC avg
§102
28.6%
-11.4% vs TC avg
§112
5.3%
-34.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1220 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement filed on 01/17/2024 has been considered and placed in the application file. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3, 6, 8-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Takeya et al. (U.S. 8,903,374). Regarding claim 1, Takeya et al. (hereinafter, Ref~374) discloses (please see Figs. 2-5 and related text for details) a power amplifier calibration process (see the power amplifier shown in Fig. 2 and the process shown Fig. 5 for details) comprising: warming up (e.g., during the start-up of the calibration operation) a power amplifier (50 and/or 52 of Fig. 2) through a plurality of dummy pulses (e.g., digital control signals provided to regulate the power supply as described in col. 7, line 30+ can broadly be read as the claimed pulses OR test tones having bit sequences as described in col. 10, line20+ can be mapped to the claimed one); and after warming up the power amplifier, sweeping through a plurality of gate voltages (test tone voltages/signals provided to gate/base of the amplifier 50 and/or amplifier 52 of Fig. 2) until a desired drain current (current generated at the drain/collector of the amplifier 50 and/or amplifier 52 of Fig. 3) is detected (please note that the generic amplifier 50 and/or 52 of Fig. 2 would obviously be employed with FET(s) having gate configured to receive input signal and drain configured to output an amplified output signal as widely-used in the field), meeting claim 1. Regarding claim 3, Ref~374 supports the claimed “wherein warming up the power amplifier through the plurality of dummy pulses comprises using a radio frequency (RF) signal generator circuit to generate a plurality of preliminary RF signal pulses” as described, for instance, in col. 11, line 25+, meeting claim 3. Regarding claim 6, Ref~374 discloses the power amplifier calibration process of claim 1, further comprising storing information (see calibration results 100 of Fig. 5) relating to a gate voltage that gives the desired drain current for subsequent use as described/shown in Fig. 5, meeting claim 6. Regarding claim 8, the circuit of Ref~374 would be capable of supporting the claimed power amplifier calibration process of claim 1, further comprising implementing the power amplifier in a radar system, since it can be employed in wireless communication devices or the like including radar system claimed (see BACKGROUNED OF THE INVENTION/col. 1), meeting claim 8. Regarding claim 9, Ref~374 discloses (please see Figs. 2-5 and related text for details) a calibration system (system of Fig. 2) comprising: a device under test (36 of Fig. 2) comprising a power amplifier (please note that the generic amplifier 50 and/or 52 of Fig. 2 would obviously be employed with at least one FET or BJT having gate/base configured to receive input signal and drain/collector configured to output amplified signal as wide-used in the field); a radio frequency (RF) signal generator circuit (44 of Fig. 2) coupled to an RF input of the power amplifier; a current sensor (72 of Fig. 2) coupled to a drain of the power amplifier; and a controller (70 and/or 68 and/or 44 of Fig. 2) configured to: receive a detection signal (76 of Fig. 2) from the current sensor; sweep a gate voltage source (disposed at input terminal of amplifier 50 and/or amplifier 52 of Fig. 2) through a plurality of values to change current at the current sensor as described, for instance, in col. 11, line 50+; interrupt delivery of an RF signal to the power amplifier during the sweep (please note that only test tones are being employed during calibration); and warm up the power amplifier through delivery of a series of dummy pulses to the power amplifier, meeting claim 9. Regarding claim 10, Ref~374 supports the claimed “wherein the controller is further configured to open a switch between the RF signal generator circuit and the power amplifier”, since”, since only test signal(s) is/are employed during calibration, thus obviating the claimed feature, meeting claim 10. Regarding claim 12, Ref~374 supports the claimed “wherein a signal from the RF signal generator circuit provides the series of dummy pulses”, since digital control signals provided to regulate the power supply as described in col. 7, line 30+ can broadly be read as the claimed pulses OR test tones having bit sequences as described in col. 10, line20+ can be mapped to the claimed one), meeting claim 12. Allowable Subject Matter Claims 2, 4-5, 7 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /HIEU P NGUYEN/Primary Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Oct 23, 2023
Application Filed
Feb 20, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603618
SIGNAL AMPLIFYING CIRCUIT AND SIGNAL PROCESSING SYSTEM AND ANALOG-TO-DIGITAL CONVERTING SYSTEM COMPRISING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12603616
POWER AMPLIFIER MODULE WITH INTERLEAVED WIREBONDS
2y 5m to grant Granted Apr 14, 2026
Patent 12597899
SWITCHING AMPLIFIER
2y 5m to grant Granted Apr 07, 2026
Patent 12597898
HIGH-FREQUENCY CIRCUIT AND COMMUNICATION DEVICE
2y 5m to grant Granted Apr 07, 2026
Patent 12597891
CASCODED HIGH-VOLTAGE AMPLIFIER
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.1%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 1220 resolved cases by this examiner. Grant probability derived from career allow rate.

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