DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites the limitation "the first pad" in lines 4 – 5. Claim 5 recites the limitation "the second pad" in lines 6 – 7. There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim s 1 – 4, 7 – 10, 12 , 14 – 16, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (US 2020/0243449) in view of Guo et al. (US 2020/0411443) . (Claim 1) Chiang et al. teach a semiconductor package, comprising: a package substrate ( 292 ) comprising a mounting region (middle) and an edge region at least partially surrounding the mounting region; a bridge chip (2 30 ) on a top surface of the mounting region of the package substrate; a first connection pad ( labelling analogous to fig. 3A #270 associated with 210) and a second connection pad ( labelling analogous to fig. 3A #270 associated with 220) on the mounting region (middle) of the package substrate and spaced apart from the bridge chip; a third connection pad ( labelling analogous to fig. 3b #240 embedded in #254) on the edge region of the package substrate; a first mold layer (254) on the package substrate and at least partially surrounding the bridge chip, the first connection pad, the second connection pad and the third connection pad; a first semiconductor chip (210) on the first connection pad and the bridge chip; a second semiconductor chip (220) on the second connection pad and the bridge chip; a conductive post (240 embedded in #250 ) on the third connection pad; and a second mold layer (250) on the first mold layer and at least partially surrounding the first semiconductor chip (210) , the second semiconductor chip (22) and the conductive post (240 embedded in #250). Chiang et al. lack wherein a first thermal expansion coefficient of the first mold layer is different from a second thermal expansion coefficient of the second mold layer. However, Guo et al. teach wherein a first thermal expansion coefficient of the first mold layer (150) is different from a second thermal expansion coefficient of the second mold layer (175, paragraph 66) for the benefit of cushioning effects of mismatched coefficients of thermal expansion (paragraph 43) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of cushioning effects of mismatched coefficients of thermal expansion . (Claim 2) Chiang et al. lack wherein the first mold layer contacts the second mold layer. However, Guo et al. teach wherein the first mold layer (175) contacts the second mold layer (150) for the benefit of cushioning effects of mismatched coefficients of thermal expansion (paragraph 43). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of cushioning effects of mismatched coefficients of thermal expansion. (Claim 3) Chiang et al. teach wherein the bridge chip ( labelling analogous to figure 1D # 130) comprises a first bridge chip pad ( labelling analogous to figure 1 D #1 3 2a ) and a second bridge chip pad (1 3 2 b ) , wherein the first semiconductor chip ( 11 0 ) is mounted on the first connection pad (170 associated with 11 0 ) and the first bridge chip pad (1 3 2a) in a flip chip manner, and wherein the second semiconductor chip (12 0 ) is mounted on the second connection pad (170 associated with 12 0 ) and the second bridge chip pad (1 3 2 b ) in a flip chip manner. (Claim 4) Chiang et al. teach t he semiconductor package, further comprising: first connection terminals ( labelling analogous to fig. 1G # 112a, 112b) connecting the first semiconductor chip (11 0 ) to the first connection pad (170 , associated with 11 0 ) and the first bridge chip pad (132a) ; and second connection terminals (122a, 122b) connecting the second semiconductor chip (121) to the second connection pad (170 associated with 121) and the second bridge chip pad (132b) , wherein the first connection terminals (112a, 112b) and the second connection terminals (122a, 122b) are in the second mold layer (150, paragraph 18) . (Claim 5) Chiang et al. teach t he semiconductor package, further comprising an interface between the first mold layer ( labelling analogous to fig. 1G # 150) and the second mold layer (154) , wherein, on the interface between the first mold layer and the second mold layer, first semiconductor chip pads (11 2b ) of the first semiconductor chip (11 0 ) contact the first pad and a first bridge chip pad (132a) of the bridge chip (130) , and second semiconductor chip pads of the second semiconductor chip contact the second pad and a second bridge chip pad of the bridge chip. (Claim 7) Chiang et al. teach wherein widths of the first connection pad ( fig. 3B #2 70 associated with 210 ) and the second pad ( 2 70 associated with 220 ) are smaller than a width of the third connection pad (fig. 3b #240 embedded in #254) . (Claim 8) Chiang et al. teach wherein an active surface ( bottom surface ) of the bridge chip ( fig. 3B #2 30) faces an active surface ( top surface ) of the first semiconductor chip ( 2 10) and an active surface ( top surface ) of the second semiconductor chip ( 2 20) . (Claim 9) Chiang et al. teach wherein bridge chip pads ( labelling analogous to fig. 1G # 132a, 132b) of the bridge chip (130) are exposed to an outside of the first mold layer (154) . (Claim 10) Chiang et al. teach wherein the first connection pad (fig. 3B #270 associated with 210) , the second connection pad (fig. 3B #270 associated with 220) , and the third connection pad fig. 3B #240 embedded in #254) vertically penetrate the first mold layer ( 2 54) , wherein the first connection pad, the second connection pad, and the third connection pad are coupled to substrate (292) pads of the package substrate, and wherein the first connection pad, the second connection pad, and the third connection pad are exposed to an outside of the first mold layer ( 2 54) . (Claim 12) Chiang et al. teach the semiconductor package, further comprising: a third semiconductor chip (300, paragraph 43) on the second mold layer (250) and on a top surface of the conductive post (240) that is exposed (204e) to an outside of the second mold layer (250) , or a redistribution layer on the second mold layer and on the top surface of the conductive post that is exposed to the outside of the second mold layer. (Claim 14) Chiang et al. teach a semiconductor package, comprising: a package substrate (292) ; a bridge chip (230) on the package substrate, the bridge chip comprising at least one first bridge chip pad and at least one second bridge chip pad on a top surface of the bridge chip and horizontally spaced apart; a first mold layer (254) on the package substrate and at least partially surrounding the bridge chip, wherein the at least one first bridge chip pad and the at least one second bridge chip pad are exposed to an outside of the first mold layer; a plurality of first connection pads (fig. 3B #270 associated with 210) and a plurality of second connection pads (fig. 3B #270 associated with 2 2 0) horizontally spaced apart from the bridge chip (230) , vertically penetrating the first mold layer (254) , and coupled to the package substrate (292) , the plurality of first connection pads being between the plurality of second connection pads; a first semiconductor chip (210) on the first mold layer, and on first connection pads (270) of the plurality of first connection pads and the at least one first bridge chip (230) pad; a second semiconductor chip (220) on the first mold layer (254) , and on second connection pads (270) of the plurality of first connection pads and the at least one second bridge chip (230) pad; a second mold layer (250) at least partially surrounding the first semiconductor chip (210) and the second semiconductor chip (220); a plurality of conductive posts (270) vertically penetrating the second mold layer (250) and respectively coupled to the plurality of second connection pads; and a plurality of outer terminals (solder balls) below the package substrate (292) , wherein widths of the plurality of conductive posts (270) are smaller than widths of the plurality of second connection pads. Chiang et al. lack a second mold layer contacting the top surface of a first mold layer. However, Guo et al. teach a second mold layer (150) contacting the top surface of the first mold layer for the benefit of cushioning effects of mismatched coefficients of thermal expansion (paragraph 43). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of cushioning effects of mismatched coefficients of thermal expansion . (Claim 15) Chiang et al. lack wherein a first thermal expansion coefficient of the first mold layer is different from a second thermal expansion coefficient of the second mold layer. However, Guo et al. teach wherein a first thermal expansion coefficient of the first mold layer (150) is different from a second thermal expansion coefficient of the second mold layer (175, paragraph 66) for the benefit of cushioning effects of mismatched coefficients of thermal expansion (paragraph 43) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of cushioning effects of mismatched coefficients of thermal expansion . (Claim 16) Chiang et al. teach wherein the first semiconductor chip (210) is on the first connection pads (270) of the plurality of first connection pads and the at least one first bridge chip pad ( labelling analogous to figure 1D #132a ) , wherein the second semiconductor chip (220) is on the second connection pads (270) of the plurality of first connection pads and the at least one second bridge chip pad ( labelling analogous to figure 1D #132 b) , and wherein the semiconductor package further comprises a plurality of connection terminals in the second mold layer connecting the first semiconductor chip to the first connection pads of the plurality of first connection pads and the at least one first bridge chip pad, and connecting the second semiconductor chip to the second connection pads of the plurality of first connection pads and the at least one second bridge chip pad. (Claim 18) Chiang et al. teach the semiconductor package, further comprising an interface between the first mold layer (254) and the second mold layer (252) , wherein a plurality of first semiconductor chip pads of the first semiconductor chip (210) contact the first connection pads of the plurality of first connection pads (fig. 3B #270) and the at least one first bridge chip pad ( labelling analogous to figure 1D #132a ) , and wherein a plurality of second semiconductor chip pads of the second semiconductor chip (220) contact the second connection pads of the plurality of first connection pads and the at least one second bridge chip pad ( labelling analogous to figure 1D #132 b) . (Claim 19) Chiang et al. teach a semiconductor package, comprising: a package substrate (200) ; a device layer (250) on the package substrate; and a connection layer between the package substrate and the device layer, wherein the device layer comprises: a first mold layer (250) ; a first semiconductor chip (210) and a second semiconductor chip (220) in the first mold layer; connection terminals provided on active surfaces of the first semiconductor chip and the second semiconductor chip and exposed to an outside of the first mold layer (fig, 3B, labeling analogous to fig. 1D) ; and a conductive post (240 embedded in 250 ) vertically penetrating the first mold layer (250) , wherein the connection layer comprises: a second mold layer (254) ; a bridge chip (230) in the second mold layer, wherein each of the first semiconductor chip and the second semiconductor chip are positioned such that the active surfaces at least partially surround the bridge chip in a plan view; a plurality of first connection pads (270) vertically penetrating the second mold layer (254) and connecting the first semiconductor chip and the second semiconductor chip to the package substrate (292) ; and at least one second connection pad (240 embedded in 254) vertically penetrating the second mold layer (254) and connecting the conductive post ( 240 embedded in 25 0 ) to the package substrate, and wherein the connection terminals connect the first semiconductor chip and the second semiconductor chip to the bridge chip . Chiang et al. lack wherein a first thermal expansion coefficient of the first mold layer is different from a second thermal expansion coefficient of the second mold layer. However, Guo et al. teach wherein a first thermal expansion coefficient of the first mold layer (150) is different from a second thermal expansion coefficient of the second mold layer (175, paragraph 66) for the benefit of cushioning effects of mismatched coefficients of thermal expansion (paragraph 43). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of cushioning effects of mismatched coefficients of thermal expansion. Allowable Subject Matter Claims 6, 11, 13 , 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 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