Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the communication, filed 2/6/26.
Claims 1-20 are pending.
Response to Arguments
Applicant's arguments filed 2/6/26 have been fully considered but they are not persuasive. Applicant argues Avila does not teach or suggest that a first sister sub-block is prioritized for a multi-layer cell (MLC) flow when the PEC value of a second sister sub-block is greater than the sister sub-block threshold. This is not persuasive based on the broadest reasonable interpretation.
The claim limitation requires a calculation of a sister sub-block threshold and processing a wear leveling operation. Avila teaches determining the sister sub-block threshold by determining a threshold number for a write-erase cycle count (0037). This count is used for wear-leveling operation (0036).
The limitation of “a first sister sub-block is prioritized for a multi-layer cell flow when the PEC value of a second sister sub-block is greater than the sister sub-block threshold” is interpreted as, if the write-erase cycle count of a (sister) sub-block is greater than a determined threshold, select/prioritize another/first sub-block for a memory operation. MLC flow is broadly interpreted as an operation to the MLC memory, such as storing data.
Avila teaches data access to sub-blocks in an MLC memory (0032). Avila maintains a history of the number of write-erase cycles for each each sub-block (0036). A problem sub-block with “significant difference” in uneven wear is identified by comparing the write-erase count for that sub-block and determining if it exceeds a threshold number (0036). When this happens, corrective measure is taken and other sub-block physical locations may be assigned to store data (0036: “A difference may be considered significant if it exceeds a threshold number. When such a block is identified appropriate corrective measures may be taken, assigning physical locations to store data may be modified to prioritize sub-blocks with low wear, or to avoid sub-blocks with high wear”).
Since Avila teaches determining when an erase count of a block is greater than a threshold, select/prioritize another block to do a memory operation (storing data to MLC memory; 0032, 0036), it is maintained that Avila teaches the invention, as currently claimed. The Examiner suggests Applicant further modify the claim language to more clearly define the invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 5, 11-15, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Avila et al (US20140133232, “Avila”).
As to claim 1, 12:
Avila teaches a storage device (nonvolatile memory device/system; 0005-0007) to maintain data reliability between sub-blocks by executing wear leveling operations (perform wear-leveling; 0036-0037) such that a program-erase count (PEC) difference between sister sub-blocks is reduced, associated method of operation of the storage device (method; 0007, claims), the storage device comprises:
a memory device including blocks, at least one of which is divided into sister sub-blocks (NAND nonvolatile memory having blocks, each divided into two sub-blocks; 0002-0003, 0005-0010); and
a controller (determination circuitry for wear-leveling; 0010); to calculate a sister sub-block threshold and process a wear leveling operation (determine erase count threshold; maintain history of each sub-block include number of erase cycles, a determination is made to determination a difference exists between history of different sub-blocks, such as whether the write-erase cycle count of sub-block exceeds a threshold number; 0036-0037), wherein a destination block is selected, and a first sister sub-block is prioritized for a multi-layer cell (MLC storage; 0032) flow when the PEC value of a second sister sub-block is greater than the sister sub-block threshold (identify problem sub-block with “significant difference” in uneven wear by comparing the write-erase count for that sub-block and determining if it exceeds a threshold number. When this happens, corrective measure is taken and other sub-block physical locations may be assigned to store data; 0036).
As to claim 2, 13:
Avila teaches the sister sub-block threshold is calculated based on the memory device and the sister sub-block threshold is lower than an allowed PEC difference between the first sister sub-block and the second sister sub-block (a determination is made as to whether a significant difference exists between histories of different sub-blocks, such as, whether a difference in write-erase cycle count exceeds a threshold number; 0036-0037).
As to claim 4, 14:
Avila teaches the destination block is a hottest block on a list of hot free blocks (selected location of the available sub-blocks is prioritized with low wear; 0037).
As to claim 5, 15:
Avila teaches the PEC value associated with the second sister sub-block is greater than the sister sub-block threshold and the controller determines that the first sister sub-block is in a free block pool, the controller prioritizes allocation of the first sister sub-block for the MLC flow (selected block is one of locations available for storage; determination is made as to whether a significant difference exists between histories of different sub-blocks, determine whether a difference in write-erase cycle count exceeds a threshold number; assigning physical locations to store data may be modified to prioritize sub-blocks with low wear; 0036-0037).
As to claim 11, 18:
Avila teaches the controller allocates the destination block as a wear level MLC block (select destination sub-block for wear-leveling; 0036-0037).
Allowable Subject Matter
Claims 3, 6-10, 16, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 3, the prior art does not further suggest the storage device of claim 1, wherein the controller maintains a free block pool that includes blocks on which data may be programmed and erased and the free block pool includes a list of cold free blocks and a list of hot free blocks.
As to claim 6/16, the prior art does not further suggest the storage device of claim 1/12, wherein when the PEC value associated with the second sister sub-block is greater than the sister sub-block threshold and the controller determines that the first sister sub-block is not in a free block pool, the controller forces relocation on the first sister sub-block and prioritizes allocation of the first sister sub-block for the MLC flow.
As to claim 7, the prior art does not further suggest the storage device of claim 1, wherein by prioritizing the first sister sub-block for the MLC flow, the controller increases a rate of program-erase cycles on the first sister sub-block and increases a PEC value for the first sister sub-block.
As to claim 8, the prior art does not further suggest the storage device of claim 1, wherein by prioritizing the first sister sub-block for the MLC flow, the controller reduces a difference in PEC values associated with sister sub blocks while tackling the sub block wear leveling.
As to claim 9, the prior art does not further suggest the storage device of claim 1, wherein by prioritizing the first sister sub-block for the MLC flow, the controller allocates the first sister sub-block as one of a host hybrid single-layer cell block, a host MLC block, and a relocation MLC block.
As to claim 10/17, the prior art does not further suggest the storage device of claim 1/12, wherein the controller maintains an open block pool including a host hybrid single-layer cell block, a host MLC block, a relocation MLC block, and a wear leveling MLC block.
Claims 19-20 are allowed.
As to claim 19, the prior art does not suggest the claimed method (emphasis in italics) for maintaining data reliability between sub-blocks by executing wear leveling operations on a storage device such that a program-erase count (PEC) difference between sister sub-blocks is reduced, wherein a controller on the storage device executes the method comprising: determining that a memory device is divided into sister sub-blocks; calculating a sister sub-block threshold; maintaining a free block pool and an open block pool; selecting a destination block for wear leveling from the free block pool and allocating the destination block as a wear level block in the open block pool; and prioritizing allocation of a first sister sub-block for a multi-layer cell (MLC) flow when the PEC value of a second sister sub-block is greater than the sister sub-block threshold, wherein the first sister block is allocated as one of a host hybrid single-layer cell block, a host MLC block, and a relocation MLC block.
Claim 20 is allowable for including the limitations of claim 19, and further limitations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAN NGUYEN whose telephone number is (571)272-4198. The examiner can normally be reached M-F 7:00am -4:00pm.
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/THAN NGUYEN/Primary Examiner, Art Unit 2138
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