DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-5 are pending.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities:
-- HLT -- is abbreviated without providing full form in [0003]. Various other terms e.g. OS, CPU have similar deficiency. Applicant is requested to recite the full form of the abbreviated term at least on first use.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-5 are rejected under 35 U.S.C. 112 (b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or joint inventor regards as the invention.
The following terms lack proper antecedent basis:
-- the case of -- claim 1 lines 3, 5; claim 4 lines 4, 5; claim 5 lines 5, 6.
-- the sum of -- in claim 1 line 3; claim 4 line 2; claim 5 line 3.
-- the number of operating circuits -- in claim 2 line 3.
-- the occupancy ratio -- in claim 3 line 2.
-- the bandwidth -- in claim 3 line 3.
-- the sum of -- in claim 3 line 4.
The following claim language is not clearly understood:
Claim 1 recites “determine allocation of a resource of first hardware to sequential processes”. It is unclear if the type or amount or time or all of these are being determined. It is also unclear if the amount of second hardware or time of second hardware or both amount/time of second hardware is known at the time of determination of allocation of first hardware.
Claim 1 recites “at least one predetermined-number process”. it is unclear what is being referred by predetermined-number process i.e. is the predetermined-number referring to the identity of process or predetermined order of the process in the sequence of processes or a predetermined number of processes.
Claim 1 recites “process among the sequential processes for the case where the first hardware executes….for the case where second hardware that underperforms”. It is unclear if the same process or same data is being processed by the two hardware. It is also unclear if the first and second hardware are connected in sequence or in parallel/alternative to each other.
Claim 1 recites “sum of an absolute difference between an output timing of at least one predetermined process among the sequential process”. At least two processes need to be considered for performing a sum.
Claim 1 recites “first/second hardware” without clearly reciting what are these hardware resources e.g. processor, storage, memory
Claim 2 recites “ number of operating circuits”. It is unclear “operating circuit” is referring to what e.g. cpu, processor of first hardware.
Claim 2 recites “determine the number of operating circuits to be allocated” and later recites “the number of the allocated circuits is minimized”. It is unclear what is the difference between the determined number and minimized number and what causes number to be different.
Claim 3 recites “occupancy ratio of an individual operating circuit … or the bandwidth of a communication channel”. It is unclear occupancy ratio is ratio of which two parameter.
Claims 4 and 5 recite elements of claim 1 and have similar deficiency as claim 1. Therefore, they are rejected for the same rational.
* Applicant is advised to at least indicate support present in the specification for further defining/clarifying the claim language in case Applicant believe amendments would unduly narrow the scope of the claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 4-5 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more or integrating into practical application.
claims 1, 4-5 are determined to be directed to an abstract idea. Examples of abstract ideas include at least Mathematical concepts, Mental process and Certain Methods of organizing human activity. Independent claim 1 is directed to “determining allocation of first hardware resource for a particular process of plurality of processes being sequentially processed, such that sum of difference between timings of output of the particular process for the first hardware and a underperforming second hardware is within a predetermined tolerance ” at a high level of generality.
Step 1
As described in MPEP § 2106, subsection III, Step 1 of the eligibility analysis asks: Is the claim to a process, machine, manufacture or composition of matter?
Claim 1 recites a resource management device comprising a processor, which falls within the “machine / manufacture” category of 35 U.S.C. § 101. Claim 4 recites a method, which falls within the “process” category of 35 U.S.C. § 101. Claim 5 recites a non-transitory recording medium”, which falls within the “machine / manufacture” category of 35 U.S.C. § 101.Thus, the analysis determines whether the claims recite a judicial exception and fail to integrate the exception into practical application. See Memorandum, 84 Fed. Re. 54-55. If both elements are satisfied, the claims are directed to a judicial exception under the first step of the Alice/Mayo test, See id.
Step 2A Prong One
As described in MPEP § 2106, subsection III, Step 2A of the Office’s eligibility analysis is the first part of the Alice/Mayo test, i.e., the Supreme Court’s "framework for distinguishing patents that claim laws of nature, natural phenomena, and abstract ideas from those that claim patent-eligible applications of those concepts." Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 217-18, 110 USPQ2d 1976, 1981 (2014) (citing Mayo, 566 U.S. at 77-78, 101 USPQ2d at 1967-68).
Step 2A is a two-prong inquiry, in which examiners determine in Prong One whether a claim recites a judicial exception, and if so, then determine in Prong Two if the recited judicial exception is integrated into a practical application of that exception.
claim elements
i
A resource management device comprising: a processor configured to
generic device
ii
determine allocation of a resource of first hardware to sequential processes so that the sum of an absolute value of a difference between an output timing of at least one predetermined-number process among the sequential processes for the case where the first hardware executes the sequential processes and an output timing of the predetermined-number process for the case where second hardware that underperforms the first hardware executes the sequential processes is within a predetermined tolerance.
Mental process abstract idea
Claim 1 step [ii] describes “concepts performed in the human mind” or “observation, evaluation, judgement, opinion.” Claim 1 step [ii] is directed to “determining hardware resource allocation of a process such that the sum of time difference of output of the two different hardware processing in sequence is within a predetermined tolerance”, which is a combination of observation, evaluation, judgement and opinion, and may be performed by human mind, according to the broadest reasonable interpretations of the claim elements and can be performed by human mind alone or with the aid of pen and paper. The courts consider a mental process (thinking) that "can be performed in the human mind, or by a human using a pen and paper" to be an abstract idea. CyberSource Corp. v. Retail Decisions, Inc., 654 F.3d 1366, 1372, 99 USPQ2d 1690, 1695 (Fed. Cir. 2011).
Thus, claim 1 recites a judicial exception. For these same reasons, claims 4-5 also recites judicial exception.
Step 2A, Prong Two
As described in MPEP § 2106, subsection III, Step 2A of the Office’s eligibility analysis is the first part of the Alice/Mayo test, i.e., the Supreme Court’s "framework for distinguishing patents that claim laws of nature, natural phenomena, and abstract ideas from those that claim patent-eligible applications of those concepts." Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 217-18, 110 USPQ2d 1976, 1981 (2014) (citing Mayo, 566 U.S. at 77-78, 101 USPQ2d at 1967-68).
Step 2A is a two-prong inquiry, in which examiners determine in Prong One whether a claim recites a judicial exception, and if so, then determine in Prong Two if the recited judicial exception is integrated into a practical application of that exception.
Because claims 1, 4 and 5 recite a judicial exception, analysis determines if the claims recites additional elements that integrate the judicial exception into practical application. In addition to the limitations of claim 1 discussed above that recite the mental process abstract idea, claim 1 also recites additional step [i]. Claim 1 in step [i] recites “resource management device comprising a processor configured to”. A device comprising a processor is considered a generic computing system/component and is
not be considered an improvement in the functioning of a computer or technology or technical field. See MPEP § 2106.04(d). therefore, additional claim element recites in claim 1 step [i] does not integrate the abstract idea into practical application. The Specification doesn’t provide additional details that would distinguish the additional limitations recited in claim 1 step [i] from a generic implementation of the mental process abstract idea. Thus, the claim elements recited in step [i], under broadest reasonable interpretation, do not integrate the judicial exception into a practical application.
Thus, claim 1 recites a judicial exception without integrating into practical application. For these same reasons and based on similar analysis as above, claims 4 and 4 also recite judicial exception without integrating into practical application.
Step 2B
As described in MPEP § 2106, subsection III, Step 2B of the Office’s eligibility analysis is the second part of the Alice/Mayo test, i.e., the Supreme Court’s "framework for distinguishing patents that claim laws of nature, natural phenomena, and abstract ideas from those that claim patent-eligible applications of those concepts." Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 217, 110 USPQ2d 1976, 1981 (2014) (citing Mayo, 566 U.S. 66, 101 USPQ2d 1961 (2012)).
Step 2B asks: Does the claim recite additional elements that amount to significantly more than the judicial exception.
Because claims 1, 4 and 5 are directed to judicial exception, analysis must determine, according to Alice, whether these claims recite an element, or combination of elements that is enough to ensure that the claim is directed to significantly more than a judicial exception.
The Memorandum, Section III (B) (footnote 36) states:
In accordance with existing guidance, an Examiner’s conclusion that an additional element (or combination of elements) is well understood, routine, conventional activity must be supported with a factual determination. For more information concerning evaluation of well-understood, routine, convention activity, see MPEP 2106.05(d), as modified by the USPTO Berkheimer Memorandum.
The Berkheimer Memorandum, Section III(A)(1) states:
A Specification demonstrates the well-understood, routine, conventional nature of additional elements when it describes the additional elements as well-understood or routine or conventional (or an equivalent term), as a commercially available product, on in a manner that indicates that the additional elements are sufficiently well-known that the specification does not need to describe the particulars of such additional elements to satisfy 35 §U.S.C. 112(a). A finding that an element is well-understood, routine, or conventional cannot be based only on the fact that the specification is silent with respect to describing such element.
Regarding the device, processors memories as recited in claim 1 step [i], the conventional or generalized function terms by which the computer components are described reasonably indicate that Specification discloses conventional component, and describes the component in a manner that indicates that these elements are sufficiently well-known that the Specification does not need to describe the particulars of such additional elements to satisfy 35 U.S.C. §112(a). Further, the Specification does not provide additional details that would distinguish the recited components from generic implementation in the combination. As such these additional claim elements are not directed to anything beyond conventional nature of these elements or otherwise more than well-understood, routine, conventional activity in the field of computing. These limitations either alone or in combination simply append well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception. Therefore, claim 1 doesn’t recited additional elements that amount to significantly more/
Thus, Claims 1, 4 and 5 are directed to mental process abstract idea without integrating into practical application or amount to significantly more than a patent ineligible concept.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Branson et al. (US 2014/0089929 A1, hereafter Branson) in view of Branson.
As per claim 1, Branson teaches the invention substantially as claimed including a resource management device comprising ([0001] stream processing fig. 1 management system 105):
a processor configured to determine allocation of a resource of first hardware to sequential processes ([0033] fig. 5 processing elements, compute nodes 110 A, processing element, one or more stream operators fused together to form an independently running process)
so that the sum of an absolute value of a difference between ([0043] stream operator, check, requirements, time-based criterion, in the operator graph longer than a specified amount of time or exceeds a threshold period of time)
an output timing of at least one predetermined-number process among the sequential processes for the case where the first hardware executes the sequential processes ([0034] fig. 5 processing elements, compute nodes 110 A, compute node 110B) and
an output timing of the predetermined-number process for the case where second hardware that underperforms the first hardware executes the sequential processes ([0034] fig. 5 processing elements, compute node 110C) is within a predetermined tolerance ([0043] stream operator, check, requirements, time-based criterion, in the operator graph longer than a specified amount of time or exceeds a threshold period of time i.e. also indicates when it is within the threshold [0046] maximum duration of time within which a stream operator, required to complete its processing).
Branson doesn’t specifically teach second hardware that underperforms.
Branson, however, teaches stream operator performance requirement condition is violated ([0046]) or abort processing if determination is not made within a specified time [0052]).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to have realized that the violation of performance requirement condition and/or determination is not made within the specified time is similar to the idea of underperforming hardware.
Claim 4 recites method for resource management for elements similar to claim 1. Therefore, it is rejected for the same rationales.
Claim 5 recites non-transitory medium that stores a program for resource management for elements similar to claim 1. Therefore, it is rejected for the same rationales.
Claims 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Branson, as applied to above claims, and further in view of Costa et al. (US 2023/0145437 A1, hereafter Costa).
As per claim 2, Branson teaches wherein the first hardware comprises a plurality of operating circuits (fig. 5 computing node 110A processing elements PE1-PE3 computing node 110B PE4-PE6), and the processor is further configured to determine the number of operating circuits to be allocated to the sequential processes among the plurality of operating circuits ([0044] the indication may instruct particular stream operators that the tuples are to remain in the data stream with limited processing, limited processing is a situation in which a stream operator is configured with a plurality of processing operations, and less than all of this plurality of operations is to be skipped) so that output timings of the sequential processes for the case where the first hardware executes the sequential processes are earlier than output timings ([0043] checking, time-based criterion, tuple has been in the operator graph longer than a specified threshold i.e. also indicates when it is within the threshold ) of corresponding processes for the case where the second hardware executes the sequential processes (fig. 5 computing node 110C PE7-PE8 ), and that the number of the allocated operating circuits is minimized ([0044] stream operator with limited processing ).
Branson doesn’t specifically teach that the number of the allocated operating circuits is minimized.
Costa, however, teaches that the number of the allocated operating circuits is minimized ([0027] scaling, calculate, thread scaling ratios e.g. minimum, indicative, variation in the number of core[0028] ).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Branson with the teachings of Costa of minimum scaling ratio indicative of variations in the number of cores to improve efficiency and allow that the number of the allocated operating circuits is minimized to the method of Branson as in the instant invention. The combination would have been obvious because applying the known method of scaling (min/max) and therefore the number of cores as taught by Costa with the teachings of Branson to yield predictable results with improved efficiency.
As per claim 3, Branson teaches wherein the processor determines at least the occupancy ratio of an individual operating circuit allocated to the sequential processes or the bandwidth of a communication channel between the first hardware and another device so that the sum of an absolute value of a difference between ([0043] stream operator, check, requirements, time-based criterion, in the operator graph longer than a specified amount of time or exceeds a threshold period of time) the output timing of the predetermined-number process for the case where the first hardware executes the sequential processes ([0034] fig. 5 processing elements, compute nodes 110 A, compute node 110B) and the output timing of the predetermined-number process for the case where second hardware that executes the sequential processes ([0034] fig. 5 processing elements, compute node 110C) is within a predetermined tolerance ([0043] stream operator, check, requirements, time-based criterion, in the operator graph longer than a specified amount of time or exceeds a threshold period of time i.e. also indicates when it is within the threshold [0046] maximum duration of time within which a stream operator, required to complete its processing).
Costa teaches remaining claim elements of at least the occupancy ratio of an individual operating circuit allocated to the sequential processes ([0068] ratio of utilized cores to reserved cores, utilized 75% of the available cores and reserves 25% of the cores) or the bandwidth of a communication channel between the first hardware and another device ([0022] compute resources, quantified, network bandwidth [0038] resource aware workload scheduling, resource demand, identified compute resource, bandwidth).
Examiners Note
Applicant is further reminded of that the cited paragraphs and in the references as applied to the claims above for the convenience of the applicant(s) and although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider all of the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Authorization for Internet Communication
Applicant is encouraged to submit an authorization to communicate with the Examiner via the internet by making the following statement (MPEP 502.03)
“Recognizing that internet communications are not secure, I hereby authorize the USPTO to communicate with the undersigned and practitioners in accordance with 37 CFR 1.33 and 37 CFR 1.34 concerning any subject matter of this application by video conferencing, instant messaging, or electronic mail. I understand that a copy of these communications will be made of record in the application file.”
Please note that the above statement can only by submitted via Central Fax (not Examiner’s Fax), Regular postal mail, or EFS Web using PTO/SB/439.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABU ZAR GHAFFARI whose telephone number is (571)270-3799. The examiner can normally be reached on Monday-Thursday 9:00 - 17:00 Hrs.
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/ABU ZAR GHAFFARI/Primary Examiner, Art Unit 2195