DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 13 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Publication No. 2023/0180466 Hsiao.
1. Referring to claim 13, Hsiao teaches a semiconductor device of comprising: a semiconductor substrate, (Figure 1 #10); a device isolation layer, (Figure 1 #11a & b), disposed in the semiconductor substrate, (Figure 1 #10), and defining active regions, (Figure 1 #10 & 10a); a first gate trench, (Figure 1 #14), having a first trench section provided in the active regions, (Figure 1 #10 & 10a), and having a first depth, (Figure 1 #14); a second gate trench, (Figure 1 #12), having a second trench section provided in the device isolation layer and having a second depth, (Figure 1 #12), greater than the first depth, (Figure 1 #14); a first gate structure in the first trench section, (Figure 1 #14); and a second gate structure in the second trench section, (Figure 1 #12), wherein the second gate structure, (Figure 1 #12), includes a lower portion positioned at a level lower than a bottom surface of the first trench section, (Figure 1 #12), and an upper portion on the lower portion, and wherein the device isolation layer, (Figure 1 #11a & b), includes: a low-k dielectric pattern, (Figure 1 #11a & Paragraph 0052), between the active regions, (Figure 1 #10 & 10a), and the lower portion of the second gate structure, (Figure 1 #12); and a liner insulating pattern, (Figure 1 #11b), between the active regions, (Figure 1 #10 & 10a), and the upper portion of the second gate structure, (Figure 1 #12).
2. Referring to claim 15, Hsiao teaches a semiconductor device of claim 13, wherein the device isolation layer, (Figure 1 #11a & b), includes a first portion, (Figure 1 lower portion of #11a & b), having a first width between the active regions, (Figure 1 #10 & 10a), adjacent to each other in a first direction and a second portion having a second width, (Figure 1 total width of the upper portion of #11a & b), greater than the first width, (Figure 1 lower portion of #11a & b), between the active regions, (Figure 1 #10 & 10a), adjacent to each other in a second direction, and wherein the second gate structure, (Figure 1 #12), is disposed in the second portion of the device isolation layer, (Figure 1 upper portion of #11a & b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2021/0126090 Kim et al.
3. Referring to claim 1, Kim et al. teaches a semiconductor device comprising: a semiconductor substrate, (Figure 2 #100), having a device isolation trench, (Figure 2 area of #110 & 130), defining active regions, (Figure 2 #AR); a device isolation layer, (Figure 2 #110 & 130), disposed in the device isolation trench, (Figure 2 area of #110 & 130); gate trenches, (Figure 2 #120 MG & PG), extending in a first direction with each gate trench, (Figure 10 #44), crossing a respective plurality of the active regions, (Figure 2 #AR), of the semiconductor substrate, (Figure 2 #100), and the device isolation layer, (Figure 2 #110 & 130); and word lines disposed in the gate trenches, (Figure 2 #120 MG & PG), respectively, wherein each of the gate trenches, (Figure 2 #120 MG & PG), includes first trench sections, (Figure 2 #120 MG), in respective active regions, (Figure 2 #AR), and a second trench section, (Figure 2 #120 PG), in the device isolation layer, (Figure 2 #110 & 130), the first trench sections have a first depth, (Figure 2 #120 MG), and the second trench section has a second depth, (Figure 2 #120 PG), greater than the first depth, (Figure 10 middle #44), wherein the device isolation layer, (Figure 2 #110 & 130), includes a lower portion, (Figure 2 #110), positioned at a level lower than bottom surfaces of the first trench sections, (Figure 2 #120 MG), and an upper portion, (Figure 2 #130), on the lower portion, (Figure 2 #110), but is silent to the specific combination of wherein the lower portion of the device isolation layer is formed of a dielectric material having a lower dielectric constant than that of the upper portion.
Kim et al. teaches in Paragraph 0042 that the dielectric layer #130, which is a gate insulating layer, can be made out of a high K material that is higher than SiO. Paragraph 0027 teaches dielectric layer #110 can be made out of SiO.
The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have the dielectric constant of the gate insulating layer higher than the lower portion because having a high K dielectric for the gate insulating layer will increase the threshold voltage of the gate and reduce gate oxide breakdown, thereby increasing reliability in the device. Also, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
4. Referring to claim 9, Kim et al. teaches a semiconductor device of claim 1, wherein the active regions, (Figure 2 #AR), are spaced apart from each other and arranged two-dimensionally, and wherein the second trench section of each of the gate trenches, (Figure 2 #120 PG), is disposed between respective active regions, (Figure 2 #AR), that are adjacent to each other.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
5. Claims 2-8, 10-12, 14, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. The prior art teaches the claimed matter in the rejections above, but is silent with respect to the above teachings in combination with a semiconductor device of claim 1, wherein the device isolation layer includes: a low-k dielectric pattern covering a lower sidewall of the device isolation trench; a liner insulating pattern covering an upper sidewall of the device isolation trench; and a buried insulating pattern on the liner insulating pattern; a semiconductor device of claim 1, wherein the device isolation layer includes: a low-k dielectric pattern filling a lower portion of the device isolation trench; and a liner insulating pattern covering an upper sidewall of the device isolation trench and being disposed on the low-k dielectric pattern; a semiconductor device of claim 13, wherein an upper surface of the low-k dielectric pattern is positioned at a level lower than upper surfaces of the first and second gate structures and higher than a bottom surface of the second trench section; and/or a semiconductor device of claim 15, wherein the device isolation layer further includes a buried insulating pattern on the low-k dielectric pattern in the second portion.
7. The prior art, (U.S. Patent Application Publication No. 2021/0126090 ), teaches a semiconductor device comprising: a semiconductor substrate; a device isolation layer disposed in the semiconductor substrate and defining active regions; gate trenches extending in a first direction with each gate trench crossing a respective plurality of the active regions and the device isolation layer; word lines with each word line disposed in a respective gate trench, each of the word lines including a gate conductive pattern, a gate capping pattern on the gate conductive pattern, and a gate insulating pattern between the semiconductor substrate and the gate conductive pattern; a bit line extending in a second direction intersecting with the first direction across the word lines; a bit line contact pattern between the bit line and the active regions; wherein each of the gate trenches includes first trench sections in the active regions and a second trench section in the device isolation layer, and a recess depth of the second trench section is greater than a recess depth of the first trench sections, wherein the device isolation layer includes a lower portion positioned at a level lower than bottom surfaces of the first trench sections and an upper portion on the lower portion, but is silent to the above teachings in combination with bit line spacers disposed on sidewalls of the bit line; contact patterns disposed on the semiconductor substrate and connected to end portions of the active regions; and data storage patterns connected to the contact patterns, and wherein the lower portion is formed of a dielectric material having a lower dielectric constant than that of a material forming the upper portion.
8. These combinations have been found to not be anticipated or render obvious over the prior art, hence claims 17-20 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR A MANDALA whose telephone number is (571)272-1918. The examiner can normally be reached on M-Th 8-6:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached on 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VICTOR A MANDALA/Primary Examiner, Art Unit 2899 1/2/26