DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C 102 and 103 (or as subject to pre-AIA 35 U.S.C 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-13 are subject to review.
Claim Objections
Claim 11 is objected to because of the following informalities: The limitations are listed as (a), (b), (c) to limitation (e), i.e. claim is missing limitation (d). Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4, 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 2-3, and 5-8 are rejected as being dependent claims. Appropriate correction is required.
Claim 1 recites the limitation "the input image" in the sixth and eighth limitations. There is insufficient antecedent basis for this limitation in the claim. Clarification is required.
Claim 4 recites the limitation “the summation circuit is connected to a divider circuit“, and this limitation is unclear and indefinite. Specifically, it is unclear if the divider circuit is the same divider circuit as introduced in parent Claim 1, or if the divider circuit in Claim 4 is a separate divider circuit entirely. Clarification is required.
Claim 12 recites the limitation “adding together all outputs of the subtraction absolute block by the summation circuit“, and this limitation is unclear and indefinite. Specifically, it is unclear if the outputs are produced from the same subtraction absolute block, or if the outputs are the outputs which are produced the plurality of subtraction absolute blocks from the previous limitation. Further, Claim 12 recites the limitation "the summation circuit" in limitation (c). There is insufficient antecedent basis for this limitation in the claim. Clarification is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 9-13 are rejected under 35 U.S.C 101 because the claimed invention is directed to an abstract idea without reciting significantly more.
Step 1 – is the claim directed to a process, machine, manufacture, or composition of matter?
Claims 9-13 are directed to a “method” which describes one of the four statutory categories of patentable subject matter, i.e., a process.
Regarding Claim 9
Steps 2A Prong 1 – is the claim directed to a law of nature, a natural phenomenon (product of nature) or an abstract idea?
Yes, Claim 9 recites an abstract idea, substantially as follows:
“(c) configuring each pooling layer to perform absolute average deviation pooling, wherein each pooling layer comprises one or more subtraction absolute blocks, and wherein each subtraction absolute block comprises two inputs;”– is directed to the abstract idea of mathematical concepts (See MPEP 2106.04(a)(2)) as it is describing absolute average deviation pooling, which is considered to be a mathematical calculation.
“(d) obtaining an absolute deviation from the subtraction absolute block; and” – is directed to the abstract idea of mathematical concepts (See MPEP 2106.04(a)(2)) as it is describing a mathematical calculation.
“(e) dividing the absolute deviation by 2.” – is directed to the abstract idea of mathematical concepts (See MPEP 2106.04(a)(2)) as it is describing a mathematical calculation.
Step 2A Prong 2: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No, Claim 9 does not include additional limitations that integrate the judicial exception into a practical application. The additional limitation(s):
“(a) utilizing a convolutional neural network comprising one or more convolutional layers;” – is directed to merely applying an abstract idea using a generic computer as a tool, considered mere instruction apply an exception (see MPEP 2106.05(f)(2), 2106.04(d)).
“(b) inserting a pooling layer between each convolutional layer in the convolutional neural network;” – is directed to merely applying an abstract idea using a generic computer as a tool, considered mere instruction apply an exception (see MPEP 2106.05(f)(2), 2106.04(d)).
Therefore, the additional elements, alone or in combination, do not integrate the abstract idea into a practical application (See MPEP 2106.04).
Step 2B – Does the claim recite additional elements that amount to significantly more than the judicial exception?
No, Claim 9 does not include additional limitations that amount to significantly more than the judicial exception. The additional limitation(s):
“(a) utilizing a convolutional neural network comprising one or more convolutional layers;” – is directed to merely applying an abstract idea using a generic components as a tool, considered mere instruction apply an exception (see MPEP 2106.05(f)(2), 2106.04(d)).
“(b) inserting a pooling layer between each convolutional layer in the convolutional neural network;” – is directed to merely applying an abstract idea using a generic components as a tool, considered mere instruction apply an exception (see MPEP 2106.05(f)(2), 2106.04(d)).
Therefore, the additional elements, alone or in combination, do not amount to significantly more than the judicial exception (See MPEP 2106.05).
Regarding Claim 10
Steps 2A Prong 1 – is the claim directed to a law of nature, a natural phenomenon (product of nature) or an abstract idea?
No, Claim 10 does not recite an abstract idea.
Step 2A Prong 2: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No, Claim 10 does not include additional limitations that integrate the judicial exception into a practical application. The additional limitation(s):
“(a) a subtraction operator; (b) a comparator circuit; (c) a multiplication operator; and (d) a buffer.” – is directed to merely applying an abstract idea using a generic components as a tool, considered mere instruction apply an exception (see MPEP 2106.05(f)(2), 2106.04(d)).
Therefore, the additional elements, alone or in combination, do not integrate the abstract idea into a practical application (See MPEP 2106.04).
Step 2B – Does the claim recite additional elements that amount to significantly more than the judicial exception?
No, Claim 10 does not include additional limitations that amount to significantly more than the judicial exception. The additional limitation(s):
“(a) a subtraction operator; (b) a comparator circuit; (c) a multiplication operator; and (d) a buffer.” – is directed to merely applying an abstract idea using a generic components as a tool, considered mere instruction apply an exception (see MPEP 2106.05(f)(2), 2106.04(d)).
Therefore, the additional elements, alone or in combination, do not amount to significantly more than the judicial exception (See MPEP 2106.05).
Regarding Claim 11
Steps 2A Prong 1 – is the claim directed to a law of nature, a natural phenomenon (product of nature) or an abstract idea?
Yes, Claim 11 recites an abstract idea, substantially as follows:
“(a) applying a subtraction operation to the two inputs to obtain an output, and wherein the output is connected to two routes,” – is directed to the abstract idea of mathematical concepts (See MPEP 2106.04(a)(2)) as it is describing subtraction operation which is considered to be a mathematical calculation.
“(c) comparing the output to a threshold value by the comparator circuit, wherein: a. if comparison by the comparator circuit produces a positive result, the comparator circuit provides a positive 1 as its output; b.if comparison by the comparator circuit produces a negative result, the comparator circuit produces a negative 1 as its output;” – is directed to the abstract idea of mathematical concepts (See MPEP 2106.04(a)(2)) as it is describing comparison with a threshold value, which is considered to be a mathematical relationship.
“(e) multiplying the comparator circuit output with the buffer output to obtain an absolute deviation.” – is directed to the abstract idea of mathematical concepts (See MPEP 2106.04(a)(2)) as it is describing a mathematical calculation.
Step 2A Prong 2: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No, Claim 11 does not include additional limitations that integrate the judicial exception into a practical application. The additional limitation(s):
“wherein one route is connected to a buffer and the other route is connected to a comparator circuit;” – is directed to merely applying an abstract idea using a generic components as a tool, considered mere instruction apply an exception (see MPEP 2106.05(f)(2), 2106.04(d)).
“(b) buffering the output by the buffer;” – is merely a recitation of an insignificant extra-solution data outputting (see MPEP 2106.05(g)).
Therefore, the additional elements, alone or in combination, do not integrate the abstract idea into a practical application (See MPEP 2106.04).
Step 2B – Does the claim recite additional elements that amount to significantly more than the judicial exception?
No, Claim 11 does not include additional limitations that amount to significantly more than the judicial exception. The additional limitation(s):
“wherein one route is connected to a buffer and the other route is connected to a comparator circuit;” – is directed to merely applying an abstract idea using a generic components as a tool, considered mere instruction apply an exception (see MPEP 2106.05(f)(2), 2106.04(d)).
“(b) buffering the output by the buffer;” – the broadest reasonable interpretation of this imitation is found to be merely outputting data, which is analogous to receiving or transmitting data over a network, considered WURC under MPEP2106.05(d)(II)(i).
Therefore, the additional elements, alone or in combination, do not amount to significantly more than the judicial exception (See MPEP 2106.05).
Regarding Claim 12
Steps 2A Prong 1 – is the claim directed to a law of nature, a natural phenomenon (product of nature) or an abstract idea?
Yes, Claim 12 recites an abstract idea, substantially as follows:
“(c) adding together all outputs of the subtraction absolute block by the summation circuit.” – is directed to the abstract idea of mathematical concepts (See MPEP 2106.04(a)(2)) as it is describing a mathematical calculation.
Step 2A Prong 2: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No, Claim 12 does not include additional limitations that integrate the judicial exception into a practical application. The additional limitation(s):
“(a) operating the subtraction absolute blocks in parallel;” – is directed to merely applying an abstract idea using a generic components as a tool, considered mere instruction apply an exception (see MPEP 2106.05(f)(2), 2106.04(d)).
“(b) obtaining an output of each subtraction absolute block; and” – is merely a recitation of an insignificant extra-solution data gathering (see MPEP 2106.05(g)).
Therefore, the additional elements, alone or in combination, do not integrate the abstract idea into a practical application (See MPEP 2106.04).
Step 2B – Does the claim recite additional elements that amount to significantly more than the judicial exception?
No, Claim 12 does not include additional limitations that amount to significantly more than the judicial exception. The additional limitation(s):
“(a) operating the subtraction absolute blocks in parallel;” – is directed to merely applying an abstract idea using a generic components as a tool, considered mere instruction apply an exception (see MPEP 2106.05(f)(2), 2106.04(d)).
“(b) obtaining an output of each subtraction absolute block; and” – the broadest reasonable interpretation of this imitation is found to be merely receiving data, which is analogous to receiving or transmitting data over a network, considered WURC under MPEP2106.05(d)(II)(i).
Therefore, the additional elements, alone or in combination, do not amount to significantly more than the judicial exception (See MPEP 2106.05).
Regarding Claim 13
Steps 2A Prong 1 – is the claim directed to a law of nature, a natural phenomenon (product of nature) or an abstract idea?
Yes, Claim 13 recites an abstract idea, substantially as follows:
“further comprising applying a sliding window algorithm.” – is directed to the abstract idea of mathematical concepts (See MPEP 2106.04(a)(2)) as it is describing an algorithm, which is considered to be a mathematical calculation.
Step 2A Prong 2: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No, Claim 13 does not include additional limitations that integrate the judicial exception into a practical application.
Step 2B – Does the claim recite additional elements that amount to significantly more than the judicial exception?
No, Claim 13 does not include additional limitations that amount to significantly more than the judicial exception.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 4, 6, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Singh et al (US 20210264250 A1), hereinafter referred to as Singh, in view of Liu et al (US 20240053962 A1), hereinafter referred to as Liu, and further in view of Hoefler et al (US 20220244911 A1), hereinafter referred to as Hoefler.
Regarding Claim 1
Singh discloses:
“a multi-layer perceptron classifier;” (Singh at [0029]: The input data 110 is provided to the input layer 120 and is passed through the various convolution layers 104 and the fully connected layers 121. The output of the final fully connected layer is the prediction data 112) [Examiner Note: multiple fully connected layers are equivalent to a multi-layer perceptron]
“two or more convolutional layers; and two or more pooling layers;” (Singh at [0029] FIG. 2 is a simplified block diagram of process flow within a CNN 102, according to one embodiment. The CNN 102 includes an input layer 120, a plurality of convolution layers 105, and one or more connected layers 121; Singh at Fig. 2
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“wherein the input image is fed into one convolutional layer, and an output of the convolutional layer is fed into a pooling layer;” (Singh at [0022]: Accordingly, the input data 110 can include image data corresponding to one or more images captured by the image sensor. The image data is formatted so that it can be received by the CNN 102; Singh at [0029]: The input data 110 is provided to the input layer 120 and is passed through the various convolution layers 104 and the fully connected layers 121; Singh at [0032]: Pooling operations 107 are performed on the feature data between each convolution layer [Examiner Note: mapped to output of convolutional layer is fed in to a pooling layer]. As described above, the pooling operations reduce the dimensionality of the feature data by performing arithmetic operations on the feature data)
“wherein each pooling layer comprises at least one […] block and” (Singh at Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations [Examiner Note: mapped to pooling layer] between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.)
“wherein the input image is fed into a second convolutional layer, and an output of the second convolutional layer is fed into a second pooling layer; and wherein a sequencing of convolutional layer to pooling layer is repeated through a fully connected layer;” (Singh at [0029]: The input data 110 is provided to the input layer 120 and is passed through the various convolution layers 104 and the fully connected layers 121; Singh at [0033]: This processes of convolution and pooling repeat until the final convolution layer 107 has performed convolution operations on the received feature data. Pooling operations 107 are performed on the feature data from the final convolution layer 105. The feature data is then provided to the fully connected layers 122)
“wherein an output of the final pooling layer is connected to the multi-layer perceptron classifier;” (Singh at [0033]: Pooling operations 107 are performed on the feature data from the final convolution layer 105. The feature data is then provided to the fully connected layers 122; Singh at Fig. 2:
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“and wherein an output of the multi-layer perceptron classifier comprises a result.” (Singh at [0033]: The fully connected layers [Examiner Note: mapped to multi-layer perceptron] 122 then generate prediction data [Examiner Note: mapped to result] 112 from the feature data)
However, Singh does not disclose:
“one subtraction absolute block and at least one divider circuit;”
On the other hand, Liu discloses:
“one subtraction absolute block” (Liu at [0016] FIG. 1 is a diagram of an illustrative integrated circuit device such as integrated circuit 10 having absolute difference circuitry 12)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Singh with the above teachings of Liu by using an architecture of a convolutional neural network as taught by Singh, and using subtraction absolute blocks and circuitry, as taught by Liu. The modification would have been obvious because one of ordinary skill in the art would be motivated to reduce area power consumption without compromising performance as suggested by Liu at [0015]: “Configured and operated in this way, the absolute difference circuitry exhibits minimal area and power consumption without degrading performance.”
However, the combination of Singh and Liu does not disclose:
“at least one divider circuit”
On the other hand, Hoeffler discloses:
“at least one divider circuit” (Hoeffler at [0039]: Divider circuit 608 may access values in buffer 604 and the summed value ΣAx to produce normalized values: Ax/ΣAx.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Singh and Liu with the above teachings of Hoefler by using an architecture of a convolutional neural network as taught by Singh and Liu, and using divider circuitry, as taught by Hoefler. The modification would have been obvious for the purpose of normalization of a model in an efficient way as suggested by Hoefler at [0004]: “The disclosure presented herein provides digital circuits and processing techniques that may be used in normalization functions (and other applications) more efficiently”, and at [0039] “In some embodiments, the normalized values are used to process neural network data, for example.”
Regarding Claim 4
The combination of Singh, Liu, and Hoefler discloses, “The architecture of Claim 1,” and the limitations are shown in the rejection above.
The combination of Singh, Liu, and Hoefler further discloses
“the pooling layer comprises two or more subtraction absolute blocks;” (Singh at Abstract: The pooling unit [Examiner Note: mapped to pooling layer] includes hardware blocks that promote computational and area efficiency in the convolutional neural network; Liu at [0016] FIG. 1 is a diagram of an illustrative integrated circuit device such as integrated circuit 10 having absolute difference circuitry 12)
“the subtraction absolute blocks comprise functionality to operate in parallel;” (Liu at [0017]: In general, integrated circuit device 10 may include multiple instances of absolute difference circuitry 12 for computing a large number of absolute difference values in a sequential or parallel manner)
“the outputs of the […] blocks are connected to a summation circuit; and the summation circuit is connected to a divider circuit.” (Hoefler at [0039]: FIG. 6 illustrates a normalization system 600 according to an embodiment. […] The values may be added together in summation circuit 606. Divider circuit 608 may access values in buffer 604 and the summed value ΣAx to produce normalized values: Ax/ΣAx. The normalized values may, for example, be coupled to a matrix multiplication circuit 610: Hoefler at Fig. 6:
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The same motivations utilized for combining Singh, Liu, and Hoefler, as set forth in Claim 1, are equally applicable to Claim 4.
Regarding Claim 6
The combination of Singh, Liu, and Hoefler discloses, “The architecture of Claim 4,” and the limitations are shown in the rejection above.
The combination of Singh, Liu, and Hoefler further discloses:
“wherein an output of the divider circuit comprises a value of non-pooled matrix values.” (Hoefler at [0039]: Divider circuit 608 may access values in buffer 604 and the summed value ΣAx to produce normalized values: Ax/ΣAx; Singh at [0070]: The feature tensor [Examiner Note: mapped to matrix values]128 or the cropped feature tensor 168 can be partially regenerated by the unpooling operation.
The same motivations utilized for combining Singh, Liu, and Hoefler, as set forth in Claim 1, are equally applicable to Claim 6.
Regarding Claim 7
The combination of Singh, Liu, and Hoefler discloses, “The architecture of Claim 4,” and the limitations are shown in the rejection above.
The combination of Singh, Liu, and Hoefler further discloses:
“further comprising functionality to perform a sliding window algorithm.” (Singh at [0063-0064]: FIG. 10 illustrates a pooling operation [Examiner Note: mapped to sliding window algorithm] performed by the pooling unit 106, according to one embodiment. The configuration registers 164 determine the size of a pooling window for each pooling operation. The pooling window corresponds to a selected portion of the cropped feature tensor 168. […] In the example of FIG. 10, the pooling window is 3×3. If the height and width of the cropped feature tensor 168 is 9×9, the selected pooling window is 3×3, and the stride is 3 (described in more detail below) then for each nonoverlapping 3×3 window of a single depth slice of the cropped feature tensor 168, a single data value will be generated by the pooling operation. This corresponds to nine data values for each 9×9 slice from the cropped feature tensor 168)
Claim(s) 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Singh in view of Liu and further in view of Hoefler and further in view of Moreland et al (US 4442544 A), hereinafter referred to as Moreland.
Regarding Claim 2
The combination of Singh, Liu, and Hoefler discloses, “The architecture of Claim 1,” and the limitations are shown in the rejection above.
The combination of Singh, Liu, and Hoefler further discloses:
“at least two inputs; an output;” (Liu at [0016] FIG. 1 is a diagram of an illustrative integrated circuit device such as integrated circuit 10 having absolute difference circuitry 12; Liu at Fig. 1:
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[Examiner Note: A and B are mapped to at least two inputs, and |A-B| is mapped to an output])
However, the combination of Singh, Liu, and Hoefler does not disclose:
“a subtraction operator; a comparator circuit; a multiplication operator; and a buffer; wherein the inputs are connected to the subtraction operator; wherein connections of an output of the subtraction operator comprises at least two routes, wherein: one route is connected to the comparator circuit; and one route is connected to the buffer; and wherein the comparator circuit output and buffer output are connected to the multiplication operator.”
On the other hand, Moreland discloses:
“a subtraction operator; a comparator circuit; a multiplication operator; and a buffer; wherein the inputs are connected to the subtraction operator; wherein connections of an output of the subtraction operator comprises at least two routes, wherein: one route is connected to the comparator circuit; and one route is connected to the buffer; and wherein the comparator circuit output and buffer output are connected to the multiplication operator.” (Moreland at Col 2, Lines 40-50: The invention further relates to an apparatus for adaptively thresholding image pixels, comprising in combination: buffer means for storing a plurality of successive ones of the pixels including the pixel to be thresholded; means for identifying the maximum pixel in the plurality of pixels; means for identifying the minimum pixel in the plurality of pixels; first subtractor means for subtracting the output of the maximum pixel identifying means from said minimum pixel identifying means; multiplier means for multiplying the output of the first subtractor means by a predetermined constant representing a desired change in threshold level; Moreland at Col 4, Lines 1-8: Minimum and maximum pixel level detection circuits 24, 26 comprise any suitable circuitry capable of identifying the minimum and maximum pixels in the block of pixels across delay buffer 12. Circuits 24, 26 for example may comprise a series of comparator circuits arranged to compare the various signal inputs thereto for the purpose of identifying the smallest (i.e. the minimum) and largest (i.e. the maximum) pixels: Moreland at Fig. 3:
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Singh, Liu, and Hoefler with the above teachings of Moreland by using an architecture of a convolutional neural network as taught by Singh, Liu, and Hoefler, and using circuitry components, as taught by Moreland. The modification would have been obvious because one of ordinary skill in the art would be motivated to improve adaptivity of thresholding image pixels suggested by Moreland at Col 1, Lines 4-8: “This invention relates to a method and apparatus for thresholding image pixels, and more particularly to an improved method and apparatus for adaptively thresholding image pixels in response to changes in image content.”
Regarding Claim 3
The combination of Singh, Liu, and Hoefler discloses, “The architecture of Claim 1,” and the limitations are shown in the rejection above.
The combination of Singh, Liu, and Hoefler does not disclose:
“wherein an additional input to the comparator circuit is a threshold value.”
On the other hand, Moreland discloses:
“wherein an additional input to the comparator circuit is a threshold value.” (Moreland at Col 4, Lines 15-20: Comparator circuit 42, which controls enabling of new threshold control gate 50, compares the difference signal output by subtractor 38 with a preset value [Examiner Note: mapped to threshold value] θ1, representing a minimum slope or rate of change in image background level, input through line 47)
The same motivation utilized for combining Singh, Liu, and Hoefler with Moreland, as set forth in Claim 2, is equally applicable to claim 3.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Singh in view of Liu and further in view of Hoefler and further in view of NPL reference Nafchi et al, “Deviation Based Pooling Strategies For Full Reference Image Quality Assessment”, hereinafter referred to as Nafchi.
Regarding Claim 5
The combination of Singh, Liu, and Hoefler discloses, “The architecture of Claim 4,” and the limitations are shown in the rejection above.
The combination of Singh, Liu, and Hoefler further discloses:
“wherein an additional input to the divider circuit comprises […]” (Hoefler at [0039]: Divider circuit 608 may access values in buffer 604 and the summed value ΣAx to produce normalized values: Ax/ΣAx.)
However, the combination of Singh, Liu, and Hoefler does not disclose:
“an average deviation value.”
On the other hand, Nafchi discloses:
“an average deviation value” (Nafchi at Pg. 2, 2.2 Mean absolute deviation (MAD) pooling:
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[Examiner Note:
L
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is mapped to an average deviation value])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Singh, Liu, and Hoefler with the above teachings of Nafchi by using an architecture of a convolutional neural network as taught by Singh, Liu, and Hoefler, and using an average deviation value, as taught by Nafchi. The modification would have been obvious because one of ordinary skill in the art would be motivated to use a faster and more reliable pooling method suggested by Nafchi at Pg. 2, Col 1, Paragraph 2: We show that the mean absolute deviation is a faster and more reliable pooling than the standard deviation for different IQAs.”
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Singh in view of Liu and further in view of Hoefler and further in view of Croxford et al (US 20230040673 A1), hereinafter referred to as Croxford.
Regarding Claim 8
The combination of Singh, Liu, and Hoefler discloses, “The architecture of Claim 4,” and the limitations are shown in the rejection above.
However, the combination of Singh, Liu, and Hoefler does not disclose:
“further comprising functionality to perform a sliding window algorithm, wherein a stride length is determined by a pooling size.”
On the other hand, Croxford discloses:
“further comprising functionality to perform a sliding window algorithm, wherein a stride length is determined by a pooling size.” (Croxford at [0052]: Example equations are set out below which define the calculations required for convolutional kernels with equal height and width (i.e. square kernels), with pooling kernels having equal height and width (i.e. square pooling), and where the stride length of the pooling kernel is equivalent to the size of the pooling kernel) [Examiner Note: pooling kernel is equivalent to window]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Singh, Liu, and Hoefler with the above teachings of Croxford by using an architecture for improving accuracy in a convolutional neural network, as taught by Singh, Liu, and Hoefler, and using a sliding window algorithm defined by pooling size as taught by Croxford. The modification would have been obvious because one of ordinary skill in the art would be motivated to optimize kernels in the processing layers of a convolutional neural network as suggested by Croxford at [0001]: “The present disclosure relates to systems, methods and apparatuses for optimizing machine learning processing. In particular, the present disclosure relates to optimizing the kernels used in processing layers of a neural network, such as a convolutional neural network.”
Claim(s) 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Singh in view of Nafchi, further in view of Liu, and further in view of Burke, Daniel (US 20240045928 A1), hereinafter referred to as Burke.
Regarding Claim 9
Singh discloses:
“(a) utilizing a convolutional neural network comprising one or more convolutional layers;” (Singh at [0029]: The CNN 102 includes an input layer 120, a plurality of convolution layers 105, and one or more connected layers 121)
“(b) inserting a pooling layer between each convolutional layer in the convolutional neural network;” (Singh at Fig. 2:
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“(c) configuring each pooling layer to perform […] pooling, wherein each pooling layer comprises one or more […] blocks,” (Singh at Abstract: The pooling unit [Examiner Note: mapped to pooling layer] performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network)
However, Singh does not disclose:
“absolute average deviation pooling”
“subtraction absolute blocks, and wherein each subtraction absolute block comprises two inputs;”
“(d) obtaining an absolute deviation from the subtraction absolute block; and”
“(e) dividing the absolute deviation by 2.”
On the other hand, Nafchi discloses:
“absolute average deviation pooling” (Nafchi at Pg. 2, 2.2 Mean absolute deviation (MAD) pooling:
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[Examiner Note: mean absolute deviation pooling is mapped to absolute average deviation pooling]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Singh, Liu, and Hoefler with the above teachings of Nafchi by using an architecture of a convolutional neural network as taught by Singh, and using absolute average deviation pooling, as taught by Nafchi. The modification would have been obvious because one of ordinary skill in the art would be motivated to use a faster and more reliable pooling method suggested by Nafchi at Pg. 2, Col 1, Paragraph 2: We show that the mean absolute deviation is a faster and more reliable pooling than the standard deviation for different IQAs.”
However, the combination of Singh and Nafchi does not disclose:
“subtraction absolute blocks, and wherein each subtraction absolute block comprises two inputs;”
“(d) obtaining an absolute deviation from the subtraction absolute block; and”
“(e) dividing the absolute deviation by 2.”
On the other hand, Liu discloses:
“subtraction absolute blocks, and wherein each subtraction absolute block comprises two inputs;” (Liu at [0016] FIG. 1 is a diagram of an illustrative integrated circuit device such as integrated circuit 10 having absolute difference circuitry 12;
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[Examiner Note: A and B are mapped to at least two inputs, and |A-B| is mapped to an output])
“(d) obtaining an absolute deviation from the subtraction absolute block; and” (Liu at [0017]: Absolute difference circuitry 12 can be configured to compute or calculate an unsigned absolute value of the difference between inputs A and B. In other words, absolute difference circuitry 12 may generate at its output port an absolute difference value equal to the magnitude |A−B|)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Singh and Nafchi with the above teachings of Liu by using an architecture of a convolutional neural network as taught by Singh and Nafchi, and using subtraction absolute blocks and circuitry, as taught by Liu. The modification would have been obvious because one of ordinary skill in the art would be motivated to reduce area power consumption without compromising performance as suggested by Liu at [0015]: “Configured and operated in this way, the absolute difference circuitry exhibits minimal area and power consumption without degrading performance.”
However, the combination of Singh, Nafchi, and Liu does not disclose:
“(e) dividing the absolute deviation by 2.”
On the other hand, Burke discloses:
“(e) dividing the absolute deviation by 2.” (Burke at [0174] In block 616, the system calculates a confidence as the absolute value of the clean score minus the dirty score (absolute difference). For normalization, the absolute difference may be divided by two)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Singh, Nafchi, and Liu with the above teachings of Burke using an architecture for improving accuracy in a convolutional neural network, as taught by Singh, Nafchi, and Liu, and dividing an absolute difference by two, as taught by Burke. The modification would have been obvious for purposes of normalization of a model in an efficient way suggested by Burke at [0174]: “For normalization, the absolute difference may be divided by two.”
Regarding Claim 13
The combination of Singh, Nafchi, Liu, and Burke discloses, “The architecture of Claim 9,” and the limitations are shown in the rejection above.
The combination of Singh, Nafchi, Liu, and Burke further disclose:
“further comprising applying a sliding window algorithm.” (Singh at [0063-0064]: FIG. 10 illustrates a pooling operation [Examiner Note: mapped to sliding window algorithm] performed by the pooling unit 106, according to one embodiment. The configuration registers 164 determine the size of a pooling window for each pooling operation. The pooling window corresponds to a selected portion of the cropped feature tensor 168. […] In the example of FIG. 10, the pooling window is 3×3. If the height and width of the cropped feature tensor 168 is 9×9, the selected pooling window is 3×3, and the stride is 3 (described in more detail below) then for each nonoverlapping 3×3 window of a single depth slice of the cropped feature tensor 168, a single data value will be generated by the pooling operation. This corresponds to nine data values for each 9×9 slice from the cropped feature tensor 168)
Claim(s) 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Singh in view of Nafchi, further in view of Liu, and further in view of Moreland.
Regarding Claim 10
The combination of Singh, Nafchi, Liu, and Burke discloses, “The architecture of Claim 9,” and the limitations are shown in the rejection above.
However, the combination of Singh, Nafchi, Liu, and Burke does not disclose:
“wherein the subtraction absolute block further comprises: (a) a subtraction operator; (b) a comparator circuit; (c) a multiplication operator; and (d) a buffer.”
On the other hand, Moreland discloses:
“wherein the subtraction absolute block further comprises: (a) a subtraction operator; (b) a comparator circuit; (c) a multiplication operator; and (d) a buffer.” (Moreland at Col 2, Lines 40-50: The invention further relates to an apparatus for adaptively thresholding image pixels, comprising in combination: buffer means for storing a plurality of successive ones of the pixels including the pixel to be thresholded; means for identifying the maximum pixel in the plurality of pixels; means for identifying the minimum pixel in the plurality of pixels; first subtractor means for subtracting the output of the maximum pixel identifying means from said minimum pixel identifying means; multiplier means for multiplying the output of the first subtractor means by a predetermined constant representing a desired change in threshold level; Moreland at Col 4, Lines 1-8: Minimum and maximum pixel level detection circuits 24, 26 comprise any suitable circuitry capable of identifying the minimum and maximum pixels in the block of pixels across delay buffer 12. Circuits 24, 26 for example may comprise a series of comparator circuits arranged to compare the various signal inputs thereto for the purpose of identifying the smallest (i.e. the minimum) and largest (i.e. the maximum) pixels: Moreland at Fig. 3:
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)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Singh, Nafchi, Liu, and Burke with the above teachings of Moreland by using an architecture of a convolutional neural network as taught by Singh, Nafchi, Liu, and Burke and using circuitry components, as taught by Moreland. The modification would have been obvious because one of ordinary skill in the art would be motivated to improve adaptivity of thresholding image pixels suggested by Moreland at Col 1, Lines 4-8: “This invention relates to a method and apparatus for thresholding image pixels, and more particularly to an improved method and apparatus for adaptively thresholding image pixels in response to changes in image content.”
Regarding Claim 12
The combination of Singh, Nafchi, Liu, and Burke discloses, “The architecture of Claim 9,” and the limitations are shown in the rejection above.
The combination of Singh, Nafchi, Liu, and Burke further disclose:
“(a) operating the subtraction absolute blocks in parallel;” (Liu at [0017]: In general, integrated circuit device 10 may include multiple instances of absolute difference circuitry 12 for computing a large number of absolute difference values in a sequential or parallel manner)
“(b) obtaining an output of each subtraction absolute block; and” (Liu at Fig. 1:
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[Examiner Note: |A-B| is mapped to an output])
However, the combination of Singh, Nafchi, Liu, and Burke does not disclose:
“(c) adding together all outputs of the […] by the summation circuit.”
On the other hand, Moreland discloses:
“(c) adding together all outputs of the […] by the summation circuit.” (Moreland at [0039]: The values may be added together in summation circuit 606)
The same motivation that was utilizing to combine Singh, Nafchi, Liu, and Burke with Moreland set forth in Claim 10 is equally applicable to Claim 12.
Allowable Subject Matter
Claim 11 would be allowable if rewritten to over the rejection(s) under 35 U.S.C 101, set forth in this office action and to include all of the limitations of the base claim and any intervening claims.
The closest prior art of record, Liu et al (US 20240053962 A1) discloses absolute difference circuitry that results in an absolute deviation value (Liu at [0004]). Additionally, Liu et al recites the absolute difference circuitry utilizing a comparator in order to produce the output at (Liu at [0029]).
However, the examiner has found that the distinct feature of the applicant’s claimed invention
over the prior art is the explicit claiming of the aforementioned limitations as specified in Claim 11.
When viewed individually or in as a combination with other prior art of record, the limitations specified
in Claim 11 are distinct.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US11263007B2 – recites a convolutional neural network hardware acceleration device with a data calculation element comprising hardware components.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMIYAH KABIR whose telephone number is (571)270-0722. The examiner can normally be reached Monday-Friday 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Yi can be reached at (571) 270-7519. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMIYAH KABIR/Examiner, Art Unit 2126
/DAVID YI/Supervisory Patent Examiner, Art Unit 2126
