DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is response to the amendment filed 8/11/2026. Claims 1-21 are pending and are under examination.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitations “N is three or more switched-capacitor branches-and inclusion of additional switched-capacitor branches improves accuracy” and “wherein N switch capacitor branches being displaced by 360/N degrees” of claims 1, 14 and 19; “the input electrical signal is converted to a digital domain before conveyance across a boundary between the first power domain and the second power domain; and wherein after passing the boundary, the input electrical signal is converted to an analog signal before the output node” of claims 13 and 21 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 1, 14 and 19, the recitation of “N is three or more switched-capacitor branches-and inclusion of additional switched-capacitor branches improves accuracy” is indefinite because it is not understood as to how the third/fourth/fifth branches (i.e., N is more than three) is realized in addition to the first two existing branches of figure 3, thus, the metes and bounds of the claim cannot be determined renders the claim indefinite.
In claims 13 and 21, the recitation of “the input electrical signal is converted to a digital domain before conveyance across a boundary between the first power domain and the second power domain; and wherein after passing the boundary, the input electrical signal is converted to an analog signal before the output node” is indefinite because it is unclear as to how signal being converted to digital and re-converted back to analog since there is no additional circuits other than the switched capacitor circuit present to perform the recited signal conversion as claimed. Thus, the metes and bounds of the claim cannot be determined renders the claim indefinite.
Claim 21 is also definite because it repeats the limitation of clam 13.
Claims 2-12, 15-18 and 20 are also indefinite because of the technical deficiencies of claims 1, 14 and 19.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 13 and 21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. In this instant, the specification has failed to describe as to how “the input electrical signal is converted to a digital domain before conveyance across a boundary between the first power domain and the second power domain; and wherein after passing the boundary, the input electrical signal is converted to an analog signal before the output node” is realized since there is no other circuits present in the claim to perform the signal conversions as claimed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-17 and 19-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chong (USP 9,503,251).
Regarding claims 1, 14 and 19, Chong’s figure 2 shows An integrated circuit, comprising an interface circuit, wherein the interface circuit comprises: an input node (255), in a first power domain (power domain of the transmitter side), configured to receive an input electrical signal (output from the transmitter side), wherein the first power domain has a first ground or reference voltage (power domain of the transmitter side, inherently has a ground potential/reference potential); an output node (270), in a second power domain (power domain of the receiver (210)), configured to output an output electrical signal (output from the interface circuit), wherein the second power domain also has a second ground or reference voltage; and a level-shifting circuit having N switched capacitor branches (upper branch switches 225 and 235; and lower branch switches 225 and 235), selectively electrically coupled to the input node and the output node, configured to perform level shifting between the first power domain and the second power domain, where N is three or more switched-capacitor branches and inclusion of the additional switched capacitor branches improve accuracy (insofar as understood, figure 7 has more than three branches when differential signaling configuration is realized. Differential signaling configuration is known less susceptible to noise than a single signal ended configuration. Thus, the limitations of “improve accuracy” is also met; see https://resources.altium.com/p/what-are-differential-pairs-and-differential-signals (cited in applicant’s remarks); discusses differential signaling configuration is less susceptible to noise than a single ended signal configuration) and wherein the level-shifting circuit comprises: a low pass filter configured to pass one or more frequencies in the input electrical signal below a first corner frequency (the first filter is a low pass switched capacitor filter (225, 250, 235, whose cutoff frequency is 3db frequency); and a high pass filter (AC coupling capacitor 205) is a high pass filter, in parallel with the multiple low pass filter, configured to pass frequencies in the input electrical signal above a second corner frequency (since it is an AC coupling capacitor, thus, it has a cutoff frequency beyond the 3db frequency); and wherein the level-shifting circuit is configured to combine outputs of the low pass filters and the high pass filter as the output electrical signal; and wherein low-frequency content of the low-pass filter is based at least in part on sampling of the N switch capacitor branches of the level shifting circuit, wherein N switch capacitor branches being displaced by 360/N degrees, at a duty cycle corresponding to the number of N switched capacitor branches of the level-shifting circuits (the low pass filter ( 225, 250, 235, 265 ) is a switched capacitor filter operated/sampled by N=2 clock signals 230 and 240; the clock signals 230 and 240 are non- overlapping (column 9, lines 15-20, figure 3A and 3C). Since the first and second pair of switches (225 and 235) cannot be switched on/off at the same time, the clock signals are complementary clock signals of 360/2= 180 degrees) as called for in claims 1, 14 and 19.
Regarding claims 2 and 15, wherein the first corner frequency equals the second corner frequency (cutoff frequencies of the low pass filter and the high pass filter).
Regarding claim 3, wherein the first corner frequency comprises a first 3 dB frequency and the second corner frequency comprises a second 3 dB frequency (the cutoff frequencies of the low pass filter and the high pass filter).
Regarding claims 4 ad 16, Chong’s figure 2 shows the low pass filter comprises a switched-capacitor circuit (225, 250, 235) and the high pass filter comprises a passive filter (AC coupling capacitor 205); and wherein the integrated circuit comprises control logic (circuit that generates clock signals controlling the switches 225 and 235) configured to provide control signals that selectively open first power domain switches (255) and selectively close second power domain switches (235) in the multi-path switched- capacitor circuit.
Regarding claim 5, Chong’s figure 2 shows the passive filter comprises an AC-coupling capacitor (205) between the first power domain and the second power domain.
Regarding claims 6 and 17, Chong’s multi-paths switch capacitor circuit (225, 250, 235) is the switched-capacitor circuit, thus, it is capable of being configured to correct DC content in the input electrical signal for a difference between the ground or 13IND0019-US reference voltages of the first power domain and the second ground or reference voltage of the second domain, and the output electrical signal comprises the corrected DC content.
Regarding claim 8, wherein the input electrical signal (output from the transmitter is a waveform function of time) and the output electrical signal (input to the receiver is a waveform function of time) have a common waveform as a function of time.
Regarding claim 9, Chong’s interface circuit designed with minimal baseline wander, thus, the limitation of wherein the level shifting between the first power domain and the second power domain is performed with a latency less than a predefined value is also met.
Regarding claims 10 and 20, Chong’s figure 6A shows the input electrical signal and the output electrical signal comprise analog electrical signals.
Regarding claim 11, Chong’s figure 6A shows the input electrical signal and the output electrical signal comprise logic signals having multiple logic levels and temporal transition points between the logic levels (logic high and logic low).
Regarding claim 12, Chong’s logic signals are associated with asynchronous logic.
Regarding claim 13, “the input electrical signal is converted to a digital domain before conveyance across a boundary between the first power domain and the second power domain; and wherein after passing the boundary, the input electrical signal is converted to an analog signal before the output node”, insofar as understood, is met by the functions of the switching pairs 225 and 235 of the switched capacitor branches.
Regarding claim 21, “the input electrical signal is converted to a digital domain before conveyance across a boundary between the first power domain and the second power domain; and wherein after passing the boundary, the input electrical signal is converted to an analog signal before the output node”, insofar as understood, is met by the functions of the switching pairs 225 and 235 of the switched capacitor branches.
Response to Arguments
Applicant's arguments filed 8/11/2026 have been fully considered but they are not persuasive. Applicant argues that Fig. 7 of Chong discloses a differential pair transmission line, which means the multiple paths in the circuit are driven by separate input signal/voltage sources that are out of phase and are not the same as the recited N switch-capacitor branches displaced by 360/N degrees. A person of ordinary skill in the art would understand a differential pair line circuit is composed of two (2) lines and not three or more, found not persuasive. As presently claimed, claims 1, 14 and 19 recites N is more than three but the disclosure does not describe as to how the third/fourth/fifth branches would fit into the existing first two branches. Furthermore, the current recited limitations in claims 1, 14 and does not exclude the differential signaling configuration shown in Chong’s figure 7. The additional third and fourth branches configured to receive an input electrical signal (output from the transmitter side), wherein the first power domain has a first ground or reference voltage (power domain of the transmitter side, inherently has a ground potential/reference potential); an output node (270), in a second power domain (vbias), configured to output an output electrical signal (output from the interface circuit), wherein the second power domain also has a second ground or reference voltage; and a level-shifting circuit having N switched capacitor branches (upper branch switches 225 and 235; and lower branch switches 225 and 235), selectively electrically coupled to the input node and the output node, configured to perform level shifting between the first power domain and the second power domain. The rejection is deemed proper. Thus, claims 1-6, 8-17 and 19-21 remain rejected.
Allowable Subject Matter
Claims 7 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Chong (USP 9,503,251), alone or in combination, fails to teach or fairly suggest wherein the low-pass filter comprises a buffer circuit configured to drive a resistor as called for in claims 7 and 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In this regard, applicant’s cited prior art has been carefully considered.
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/TUAN T LAM/Primary Examiner, Art Unit 2842 8/29/2026
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