Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3; 12, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kimura (US 5467046 A) in view of , hereafter referred to as “Kimura”.
Claims 1, 2, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US 5467046 A) in view of Suzaki (20080231368), hereafter referred to as “Kimura” and “Suzaki”, respectively.
Regarding claims 1 and 12, in the embodiments of Figs. 2 and 3, Kimura discloses:
A wide-band logarithmic power detector (Figs. 2 and 3, C-MOS logarithmic IF amplifier) comprising:
an input stage (input stage comprising amplifier A1, capacitor CA1 and rectifier B1) receiving an input signal (IF INPUT), the input stage comprising:
an input rectifier (rectifier B1) that rectifies the output signal of the input stage into an input stage DC output signal (column 1 lines 41-45, each rectifier outputs a direct-current value);
one or more cascaded stages (IF amplifiers A1-A5 are cascade-connected) cascaded together with the input stage into a stage chain,
each cascaded stage comprising:
a limiting amplifier (IF Amplifier A2) coupled in series to the input stage (as shown in Figs. 2 and 3) or a preceding cascaded stage (Figs. 2 and 3, same as the input stage), the limiting amplifier amplifies an output signal from the input stage (as shown in Figs. 2 and 3) or the preceding cascaded stage into an amplifier output signal for the each cascaded stage (as shown in Figs. 2 and 3); and
a cascaded stage rectifier (rectifier B2) that rectifies the output signal of each cascaded stage into a DC output signal of each cascaded stage; and
a linear operation circuit (adder C) that couples to the input rectifier and the cascaded stage rectifier in each cascaded stage, the linear operation circuit is a summer circuit that sums (as per claims 3 and 14) and performs a linear operation to the input stage DC output signal and the DC output signal of each cascaded stage to generate a linear output signal (column 12, lines 23-27, adder adds direct-current components outputted from the respective half-wave rectifiers), wherein .
Note: capacitor CA1 can function as a network providing impedance to the input signal to generate an output signal of the input stage (per column 6, lines 59-65); and (CA2) is coupled in series to the limiting amplifier, and receives the amplifier output signal and outputs an output signal of each cascaded stage (as shown in Kimura, Fig. 2).
However, Kimura is silent in teaching an input matching network and a matching network.
Suzaki teaches:
an input matching network (a single capacitor (such as the capacitor CA1 of Kimura, Fig. 2) is known in the art to be rendered as a matching circuit, as an evidence to prove it is well-known, refer to Suzaki (20080231368) matching circuit 74) and a matching network (e.g. capacitor CA2 in Kimura, Fig. 2).
it would then have been obvious to one having ordinary skill in the art to modify the capacitors in Kimura (Figs. 2 and 3, capacitors CA1 and CA2) to function as a matching circuit, such as the matching circuit taught by Suzaki, especially since the equivalent matching circuit in Suzaki would have performed the equivalent function as the generic matching circuit, thereby suggesting the obviousness of such a combination.
Claims 1-3, and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over the applicant’s admitted PRIOR ART in view of Adnan et al. (US 12362779 B2), hereafter referred to as “Adnan”.
Regarding claims 1, 2, 3, 12, 13, and 14, in the embodiment of Figs. 1 and 2, the difference between the PRIOR ART and the claimed invention is an input matching and a matching network coupled in series to the limiting amplifier, the matching network receives the amplifier output signal and outputs an output signal of each cascaded stage.
However, Adnan (Fig. 7) discloses a matching network in the same context (column 9 lines 56-59), to match impedances between unequal input impedances and output impedances. Furthermore, matching circuits are well known in circuit design, thereby providing that matching in the prior art would have been obvious to a person having ordinary skill in the art to include.
Allowable Subject Matter
Claims 4-11 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 4, 7, 11, 15 and 19:
the cited prior art of record, Kimura (US 5467046 A) and applicant’s admitted PRIOR ART, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “the matching network of each cascaded stage comprising:
a first pair of coupled transmission lines coupled to the differential input terminal;
a pair of DC-blocking capacitors coupled in series to the first pair of coupled transmission lines;
a second pair of coupled transmission lines coupled in series to the pair of DC-blocking capacitors;” per claims 4, 11, and 19,
“a differential output terminal coupled to the second pair of coupled transmission lines to output the output signal of each cascaded stage;
a third pair of coupled transmission lines coupled in series to the pair of DC-blocking capacitors” per claim 4, and “a buffer circuit coupled to the main amplification circuit for impedance matching to the amplified differential signal, the buffer circuit outputs the amplifier output signal for the each cascaded stage” per claims 7 and 15.
Claims 5, 6, 8-10, 16-18 and 20 are objected to due to dependence on objected claims 4, 7, 15, and 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
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/MALANE LIENG/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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