DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
1. Claims 3 and 30 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/19/26.
Claim Rejections - 35 USC § 112
The following is a quotation of the second paragraph of 35 U.S.C. 112:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
2. Claim 6 recites the limitation "the second hole and the third hole". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 5, 7, 17, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Publication No. 2024/0274769 Kim et al.
3. Referring to claim 1, Kim et al. teaches a display panel, comprising: a first substrate comprising a plurality of signal lines, (Figures 1-4 #210 & Paragraph 0059); and light-emitting assemblies, (Figures 1-4 #120 & Paragraph 0048), located on a side of the first substrate, (Figures 1-4 #210), wherein a light-emitting assembly of the light-emitting assemblies, (Figures 1-4 #120), comprises a second substrate, (Figures 1-4 #121), a drive assembly, (Figures 1-4 #125), a light-emitting chip, (Figures 1-4 #110), and connection portions, (Figures 1-4 #122, 124, & 140); the light-emitting chip, (Figures 1-4 #110), is located on a side of the second substrate, (Figures 1-4 #121), facing away from the first substrate, (Figures 1-4 #210), the drive assembly, (Figures 1-4 #125), and the light-emitting chip, (Figures 1-4 #110), are located on a same side of the second substrate, (Figures 1-4 #121), and the drive assembly, (Figures 1-4 #125), is configured to drive the light-emitting chip, (Figures 1-4 #110), to emit light, wherein the drive assembly, (Figures 1-4 #125), is electrically connected to a respective signal line of the plurality of signal lines, (Figures 1-4 #210 & Paragraph 0059), through a respective connection portion of the connection portions, (Figures 1-4 #122, 124, & 140), and the connection portion, (Figures 1-4 #122, 124, & 140), is at least partially located on a side of the second substrate, (Figures 1-4 #121), facing the first substrate, (Figures 1-4 #210).
4. Referring to claim 2, Kim et al. teaches a display panel according to claim 1, wherein the second substrate comprises a hole structure penetrating the second substrate, (Figures 1-4 #121), a connection portion of the connection portions, (Figures 1-4 #122, 124, & 140), comprises a first portion, (Figures 1-4 #140), located on a side of the second substrate, (Figures 1-4 #121), facing the first substrate, (Figures 1-4 #210), and a second portion, (Figures 1-4 #124), overlapping the hole structure, (Figures 1-4 #122), in a first direction, and the first direction is parallel to a plane where the second substrate, (Figures 1-4 #121), is located.
5. Referring to claim 4, Kim et al. teaches a display panel according to claim 2, wherein the light-emitting chip, (Figures 1-4 #110), comprises a first electrode, (Figures 1-4 #131), and a second electrode, (Figures 1-4 #132), and at least one of the first electrode, (Figures 1-4 #131), or the second electrode, (Figures 1-4 #132), does not overlap the hole structure, (Figures 1-4 #122), in a direction perpendicular to the plane where the second substrate, (Figures 1-4 #121), is located.
6. Referring to claim 5, Kim et al. teaches a display panel according to claim 4, wherein the hole structure comprises a second hole structure, (Figures 1-4 left side #122), and a third hole structure, (Figures 1-4 right side #122), and the first electrode, (Figures 1-4 #131), and the second electrode, (Figures 1-4 #122), are located between the second hole structure, (Figures 1-4 left side #122), and the third hole structure, (Figures 1-4 right side #122), in the first direction.
7. Referring to claim 7, Kim et al. teaches a display panel according to claim 2, wherein an orthographic projection of the first portion of the connection portion, (Figures 1-4 #140), on the second substrate, (Figures 1-4 #121), covers an orthographic projection of the second portion, (Figures 1-4 #124), on the second substrate, (Figures 1-4 #121).
8. Referring to claim 17, Kim et al. teaches a display panel according to claim 1, wherein the light-emitting assembly comprises a drive wafer, (Figures 1-4 #121), and the light-emitting chip, (Figures 1-4 #110), and the drive wafer comprises the second substrate, (Figures 1-4 #121), and the drive assembly, (Figures 1-4 #125).
9. Referring to claim 19, Kim et al. teaches a display device, comprising a display panel wherein the display panel comprises: a first substrate comprising a plurality of signal lines, (Figures 1-4 #210 & Paragraph 0059); and light-emitting assemblies, (Figures 1-4 #120 & Paragraph 0048), located on a side of the first substrate, (Figures 1-4 #210), wherein a light-emitting assembly, (Figures 1-4 #120), of the light-emitting assemblies comprises a second substrate, (Figures 1-4 #121), a drive assembly, (Figures 1-4 #125), a light-emitting chip, (Figures 1-4 #110), and connection portions, (Figures 1-4 #122, 124, & 140); the light-emitting chip, (Figures 1-4 #110), is located on a side of the second substrate, (Figures 1-4 #121), facing away from the first substrate, (Figures 1-4 #210), the drive assembly, (Figures 1-4 #125), and the light-emitting chip, (Figures 1-4 #110), are located on a same side of the second substrate, (Figures 1-4 #121), and the drive assembly, (Figures 1-4 #125), is configured to drive the light-emitting chip, (Figures 1-4 #110), to emit light, wherein the drive assembly is electrically connected to a respective signal line of the plurality of signal lines, (Figures 1-4 #210 & Paragraph 0059), through a respective connection portion of the connection portions, (Figures 1-4 #122, 124, & 140), and the connection portion, (Figures 1-4 #122, 124, & 140), is at least partially located on a side of the second substrate, (Figures 1-4 #121), facing the first substrate, (Figures 1-4 #210).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
10. Claims 6, 8-16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
11. The prior art teaches the claimed matter in the rejections above, but is silent with respect to the above teachings in combination with the display panel according to claim 4, wherein in a direction parallel to a plane where the display panel is located, a minimum distance from the first electrode to the second hole structure is D1, a minimum distance from the second electrode to the third hole structure is D2, and a minimum distance between the first electrode and the second electrode is L1, wherein D1, D2, and L1 satisfies:
PNG
media_image1.png
105
388
media_image1.png
Greyscale
; the display panel according to claim 2, wherein the plurality of signal lines comprise a second signal line and a third signal line, the connection portions comprises a second connection portion and a third connection portion, the second signal line supplies a power signal to the drive assembly through the second connection portion, and the third signal line supplies at least one of a data signal or a gating signal to the drive assembly through the third connection portion, wherein the second connection portion corresponds to a fourth hole structure, the third connection portion corresponds to a fifth hole structure, and a width of the fourth hole structure in the first direction is greater than a width of the fifth hole structure in the first direction; the display panel according to claim 2, wherein the plurality of signal lines comprise a first power signal line, a second power signal line, a data signal line, and a gating signal line; the first power signal line, the second power signal line, and the data signal line extend in a second direction; the gating signal line extends in a third direction; the second direction intersects the third direction; and the second direction and the third direction are parallel to the plane where the second substrate is located; the display panel according to claim 1, wherein the first substrate further comprises a first conductive layer and a second conductive layer that are insulated from each other, the first conductive layer is located on a side of the second conductive layer facing the light-emitting assemblies, and the plurality of signal lines comprise a power signal line located in the first conductive layer; the display panel according to claim 1, wherein the first substrate further comprises a first conductive layer and a second conductive layer that are insulated from each other, the first conductive layer comprises a plurality of first conductive portions, the second conductive layer comprises a second conductive portion, the second conductive portion is a planar electrode, and the second conductive layer is located on a side of the first conductive layer facing away from the light-emitting assemblies; the display panel according to claim 1, wherein the light-emitting assemblies comprise a first light-emitting assembly and a second light-emitting assembly, the first light-emitting assembly is located on a side of the second light-emitting assembly facing the first substrate, and an orthographic projection of the second light-emitting assembly on the first substrate covers an orthographic projection of the first light-emitting assembly on the first substrate, wherein the light-emitting assemblies comprise connection holes at least penetrating the second substrate; and the first light-emitting assembly comprises a first connection hole and a second connection hole, the second light-emitting assembly comprises a third connection hole and a fourth connection hole, and a connection line between the first connection hole and the second connection hole intersects a connection line between the third connection hole and the fourth connection hole; the display panel according to claim 1, wherein the drive assembly satisfies at least one of: a sidewall of the drive assembly is coplanar with a sidewall of the light-emitting chip, or a sidewall of the second substrate is coplanar with the sidewall of the drive assembly; and/or the display panel according to claim 1, wherein a display region of the display panel comprises a first region and a second region, transmittance of the first region is greater than transmittance of the second region, the first region at least partially surrounds the second region, and the second region comprises the light-emitting assembly.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR A MANDALA whose telephone number is (571)272-1918. The examiner can normally be reached on M-Th 8-6:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached on 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VICTOR A MANDALA/Primary Examiner, Art Unit 2899 5/7/26
Prosecution Insights