DETAILED ACTION
The instant application having Application No. 18/383,704 filed on 10/25/2023 is presented for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Examiner Remark
Use of the word “means” (or “step for”) in a claim with functional language creates a rebuttable presumption that the claim element is to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is invoked is rebutted when the function is recited with sufficient structure, material, or acts within the claim itself to entirely perform the recited function.
Absence of the word “means” (or “step for”) in a claim creates a rebuttable presumption that the claim element is not to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is not invoked is rebutted when the claim element recites function but fails to recite sufficiently definite structure, material or acts to perform that function.
Claim elements in this application that use the word “means” (or “step for”) are presumed to invoke 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Similarly, claim elements that do not use the word “means” (or “step for”) are presumed not to invoke 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
In this case claim limitations “a synchronization pattern detector to ....”, “shift register associated with each correlator .....”, “a comparator to….”, “an analog to digital converter to” , “a sample rate converter to….” and “a decision device…” (Claims 1, 2, 4, 12, 16 and 19) have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because they use generic placeholders coupled with functional language “detect, store, compare, generate or process…” without reciting sufficient structure to achieve the function. Furthermore, the generic placeholder is not preceded by a structural modifier.
Since the claim limitation(s) invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, claims 1, 2, 4, 12, 16 and 19 have been interpreted to cover the corresponding structure described in the specification that achieves the claimed function, and equivalents thereof.
A review of the specification shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation: (See figures 2B, 5, 12C, 12D, 15, 16 and par. 0007, 0008, 0013, 0016, 0041, 0102, 0035 of US 2025/0106795 A1).
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
If applicant does not intend to have the claim limitation(s) treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112 , sixth paragraph, applicant may amend the claim(s) so that it/they will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites/recite sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-19 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-19 of U.S. Application No. 18/373,621. Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1-19 of the U.S. Application No. 18/373,621 merely broadens the scope of the Claims 1-19 of the instant Application.
Instant Application
Copending Application 18/373,621
Claim 1
A wireless network device, comprising:
a processing unit; and
a read circuit, wherein the read circuit comprises:
an RF circuit to receive incoming data and create a plurality of data samples per data bit, each having a certain phase, wherein a number of data samples created per data bit is referred to as an oversample rate (OSR) and wherein data samples that are separated by (OSR-1) samples are referred to as a phase of the data bits and wherein there are OSR phases of the data bits;
a synchronization pattern detector to detect a synchronization pattern from a plurality of received data samples,
wherein the synchronization pattern detector comprises:
a plurality of correlators arranged in an array of rows and columns, wherein the rows of the array are associated with a particular phase of the data bits and columns of the array are associated with time; wherein each correlator processes a predetermined number of data samples which all belong to one phase and produces a partial correlation score;
a shift register associated with each correlator to store at least three values, wherein one value is referred to as a current partial correlation score, values that are stored prior to the current partial correlation score are referred to as previous partial correlation scores, and values that are stored after the current partial correlation score are referred to as future partial correlation scores, wherein there is at least one previous partial correlation score, one current partial correlation score and at least one future partial correlation score;
a plurality of summing circuits, each having an input from a shift register associated with a correlator in each column so as to create a total correlation score associated with a symbol stream; and
a comparator to compare an output from each summing circuit to a predetermined threshold to determine whether the synchronization pattern has been detected.
Claim 1
A wireless network device, comprising:
a processing unit; and
a read circuit, wherein the read circuit comprises:
an RF circuit to receive incoming data and create a plurality of data samples per data bit, each having a certain phase, wherein a number of data samples created per data bit is referred to as an oversample rate (OSR) and wherein data samples that are separated by (OSR-1) samples are referred to as a phase of the data bits and wherein there are OSR phases of the data bits;
a synchronization pattern detector to detect a synchronization pattern from a plurality of received data samples,
wherein the synchronization pattern detector comprises:
a plurality of cost function engines arranged in an array of rows and columns, wherein the rows of the array are associated with a particular phase of the data bits and columns of the array are associated with time; wherein each cost function engine processes a predetermined number of data samples which all belong to one phase and produces a partial cost value;
a shift register associated with each cost function engine to store at least three values, wherein one value is referred to as a current partial cost value, values that are stored prior to the current partial cost value are referred to as previous partial cost values, and values that are stored after the current partial cost value are referred to as future partial cost values, wherein there is at least one previous partial cost value, one current partial cost value and at least one future partial cost value;
a plurality of summing circuits, each having an input from a shift register associated with a cost function engine in each column so as to create a total cost associated with a symbol stream; and
a comparator to compare an output from each summing circuit to a predetermined threshold to determine whether the synchronization pattern has been detected.
Claim 2
wherein each correlator processes 8 data samples to generate the partial correlation score.
Claim 2
wherein each cost function engine processes 8 data samples to generate the partial cost value.
Claim 3
wherein the shift register contains one previous partial correlation score, one current partial correlation score and one future partial correlation score.
Claim 3
wherein the shift register contains one previous partial cost value, one current partial cost value and one future partial cost value.
Claim 4
wherein each correlator processes 4 data samples to generate the partial correlation score.
Claim 4
wherein each cost function engine processes 4 data samples to generate the partial cost value.
Claim 5
wherein the shift register contains two previous partial correlation scores, one current partial correlation score and two future partial correlation scores.
Claim 5
wherein the shift register contains two previous partial cost values, one current partial cost value and two future partial cost values.
Claim 6
wherein the symbol stream used by at least one of the summing circuits utilizes partial correlation scores generated by correlators using different phases.
Claim 6
wherein the symbol stream used by at least one of the summing circuits utilizes partial cost values generated by cost functions using different phases.
Claim 7
wherein inputs to at least one summing circuit are selected such that at least one gap larger than (OSR-1) samples or smaller than (OSR-1) samples exists in the symbol stream.
Claim 7
wherein inputs to at least one summing circuit are selected such that at least one gap larger than (OSR-1) samples or smaller than (OSR-1) samples exists in the symbol stream.
Claim 8
wherein, if the total correlation score associated with the at least one summing circuit that utilizes a symbol stream having at least one gap larger than (OSR-1) samples is greatest, the incoming data is transmitted at a transmit baudrate having a lower frequency than a receiver baudrate used by the wireless network device.
Claim 8
wherein, if the total cost associated with the at least one summing circuit that utilizes a symbol stream having at least one gap larger than (OSR-1) samples is lowest, the incoming data is transmitted at a transmit baudrate having a lower frequency than a receiver baudrate used by the wireless network device.
Claim 9
wherein a number of gaps larger than (OSR-1) samples in the symbol stream that resulted in a greatest correlation score is indicative of a magnitude of a difference between the transmit baudrate and the receiver baudrate used by the wireless network device.
Claim 9
wherein a number of gaps larger than (OSR-1) samples in the symbol stream that resulted in a lowest cost is indicative of magnitude of a difference between the transmit baudrate and the receiver baudrate used by the wireless network device.
Claim 10
wherein, if the total correlation score associated with the at least one summing circuit that utilizes a symbol stream having at least one gap smaller than (OSR-1) samples is greatest, the incoming data is transmitted at a transmit baudrate having a higher frequency than a receiver baudrate used by the wireless network device.
Claim 10
wherein, if the total cost associated with the at least one summing circuit that utilizes a symbol stream having at least one gap smaller than (OSR-1) samples is lowest, the incoming data is transmitted at a transmit baudrate having a higher frequency than a receiver baudrate used by the wireless network device.
Claim 11
wherein a number of gaps smaller than (OSR-1) samples in the symbol stream that resulted in a greatest correlation score is indicative of a magnitude of a difference between the transmit baudrate and the receiver baudrate used by the wireless network device.
Claim 11
wherein a number of gaps smaller than (OSR-1) samples in the symbol stream that resulted in a lowest cost is indicative of a magnitude of a difference between the transmit baudrate and the receiver baudrate used by the wireless network device.
Claim 12
wherein the read circuit comprises an analog to digital converter to generate data samples, and a sample rate converter to generate I and Q signals at an oversample rate, and a sample memory to store entries used by the synchronization pattern detector and a decision device, wherein parameters associated with the read circuit are modified based on a number of gaps different from (OSR-1) that are present in the symbol stream that resulted in a greatest correlation score.
Claim 12
wherein the read circuit comprises an analog to digital converter to generate data samples, and a sample rate converter to generate I and Q signals at an oversample rate, and a sample memory to store entries used by the synchronization pattern detector and a decision device, wherein parameters associated with the read circuit are modified based on a number of gaps different from (OSR-1) that are present in the symbol stream that resulted in a lowest cost.
Claim 13
wherein the network device modifies the parameters of the read circuit to eliminate a difference between a receiver baudrate of the wireless network device and the transmit baudrate.
Claim 13
wherein the network device modifies the parameters of the read circuit to eliminate a difference between a receiver baudrate of the wireless network device and the transmit baudrate.
Claim 14
wherein the network device modifies the parameters of the read circuit to iteratively reduce a difference between a receiver baudrate of the wireless network device and the transmit baudrate.
Claim 14
wherein the network device modifies the parameters of the read circuit to iteratively reduce a difference between a receiver baudrate of the wireless network device and the transmit baudrate.
Claim 15
wherein the network device stores an indication of a difference between a receiver baudrate of the wireless network device and the transmit baudrate for a transmitting node based on a number of gaps different from (OSR-1) that are present in the symbol stream that resulted in a greatest correlation score, and uses the indication to modify the parameters of the read circuit when a subsequent packet is received from the transmitting node.
Claim 15
wherein the network device stores an indication of a difference between a receiver baudrate of the wireless network device and the transmit baudrate for a transmitting node based on a number of gaps different from (OSR-1) that are present in the symbol stream that resulted in a lowest cost, and uses the indication to modify the parameters of the read circuit when a subsequent packet is received from the transmitting node.
Claim 16
A wireless network device, comprising:
a processing unit; and
a read circuit, wherein the read circuit comprises:
an RF circuit to receive incoming data and create a plurality of data samples per data bit, each having a certain phase, wherein a number of data samples created per data bit is referred to as an oversample rate (OSR), the RF circuit comprising an analog to digital converter (ADC) to generate data samples from the incoming data, a sample rate converter to generate I and Q signals at a desired rate, and a sample memory to store a plurality of entries;
a synchronization pattern detector to detect a synchronization pattern using the plurality of entries in the sample memory,
wherein the synchronization pattern detector computes a correlation score for each of a plurality of symbol streams, each of the plurality of symbol streams comprising a number of samples equal to a number of bits in the synchronization pattern,
wherein in a first set of symbol streams, a gap of (OSR-1) samples exists between each pair of successive samples,
wherein in a second set of symbol streams, a gap greater than (OSR-1) samples exists between at least one pair of successive samples, and
wherein in a third set of symbol streams, a gap less than (OSR-1) samples exists between at least one pair of successive samples,
and wherein the correlation score of each of the plurality of symbol streams is compared to a predetermined threshold, and wherein the synchronization pattern is detected if the correlation score of one of the plurality of symbol streams is greater than the predetermined threshold.
Claim 16
A wireless network device, comprising:
a processing unit; and
a read circuit, wherein the read circuit comprises:
an RF circuit to receive incoming data and create a plurality of data samples per data bit, each having a certain phase, wherein a number of data samples created per data bit is referred to as an oversample rate (OSR), the RF circuit comprising an analog to digital converter (ADC) to generate data samples from the incoming data, a sample rate converter to generate I and Q signals at a desired rate, and a sample memory to store a plurality of entries;
a synchronization pattern detector to detect a synchronization pattern using the plurality of entries in the sample memory,
wherein the synchronization pattern detector computes a cost for each of a plurality of symbol streams, each of the plurality of symbol streams comprising a number of samples equal to a number of bits in the synchronization pattern,
wherein in a first set of symbol streams, a gap of (OSR-1) samples exists between each pair of successive samples,
wherein in a second set of symbol streams, a gap greater than (OSR-1) samples exists between at least one pair of successive samples, and
wherein in a third set of symbol streams, a gap less than (OSR-1) samples exists between at least one pair of successive samples,
and wherein the cost of each of the plurality of symbol streams is compared to a predetermined threshold, and wherein the synchronization pattern is detected if the cost of one of the plurality of symbol streams is less than the predetermined threshold.
Claim 17
wherein a frequency of a sample clock used by the ADC to generate the plurality of data samples is modified based on which of the plurality of symbol streams resulted in detection of the synchronization pattern.
Claim 17
wherein a frequency of a sample clock used by the ADC to generate the plurality of data samples is modified based on which of the plurality of symbol streams resulted in detection of the synchronization pattern.
Claim 18
wherein a rate at which the I and Q signals are generated by the sample rate converter is adjusted based on which of the plurality of symbol streams resulted in detection of the synchronization pattern.
Claim 18
wherein a rate at which the I and Q signals are generated by the sample rate converter is adjusted based on which of the plurality of symbol streams resulted in detection of the synchronization pattern.
Claim 19
wherein the read circuit comprises a decision device to further process the data samples, wherein entries from the sample memory that are provided to the decision device are selected based on which of the plurality of symbol streams resulted in detection of the synchronization pattern.
Claim 19
wherein the read circuit comprises a decision device to further process the data samples, wherein entries from the sample memory that are provided to the decision device are selected based on which of the plurality of symbol streams resulted in detection of the synchronization pattern.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALI N PASCUAL PEGUERO whose telephone number is (571)272-4691. The examiner can normally be reached Monday-Friday 11AM-9PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ASAD M NAWAZ can be reached on (571)272-3988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATALI PASCUAL PEGUERO/Examiner, Art Unit 2463
/ASAD M NAWAZ/Supervisory Patent Examiner, Art Unit 2463
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