DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
2. Claim 19 is objected to because of the following informalities: claim 19, on the last line, recites: “a protective layer on the first electrode at the first surface of the light emitting layer” which should be amended to “a protective layer on the first electrode and at the first surface of the light emitting layer” for readability.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1-7, 10, 12-13 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. U.S. Patent Application Publication 2020/0144233 A1 (the ‘233 reference, of record and matured into U.S. Patent 11,476,236 B2).
The reference discloses in Figs. 1A-1C, 2A-2C, para [30-33] (paragraph(s) [0030]-[0033]), and other text a semiconductor light emitting device and a display device as claimed.
Referring to claim 1, the reference discloses a semiconductor light emitting device, comprising:
a light emitting layer (LE1, LE2, and/or LE3, para [64]);
a passivation layer (dielectric IDL or dielectric IDL/ horizontal portion of protection layer PRT (IDL/PRT), para [96, 61]) on an upper surface and a side surface of the light emitting layer (LE1, LE2, and/or LE3);
a protective layer (passivation layer PVT, see also Fig. 12B, para [99]) on a lower surface and the side surface of the light emitting layer (LE1, LE2, and/or LE3);
a first electrode (contact/ extended pattern CT3/EL3, Fig. 2B, para [72]) between the light emitting layer (LE1, LE2, and/or LE3) and the protective layer (PVT); and
a second electrode (ohmic contact 108 (para [65-66, 68]) or contact CT1 (para [72])) between the light emitting layer (LE1, LE2, and/or LE3) and the passivation layer (IDL or IDL/PRT, (“between” is broadly interpreted, as in “The Atlantic Ocean is between Europe and the Americas” or as in “Delaware is between Main and Virginia”)),
wherein an inner angle between the side surface and the lower surface of the light emitting layer (LE1, LE2, and/or LE3) has an obtuse angle (as clearly depicted in Figs. 2B and 2C).
Referring to claim 2, Fig. 2B depicts that an inner angle between the side surface and the upper surface of the light emitting layer (LE1, LE2, and/or LE3) has an acute angle.
Referring to claim 3, the reference further discloses that the first electrode (CT3/EL3) comprises a plurality of conductive layers (CT3, EL3) on the lower surface of the light emitting layer (LE1, LE2, and/or LE3), and wherein at least one or more conductive layer (EL3) among the plurality of conductive layers is disposed on the side surface of the light emitting layer.
Referring to claim 4, for the semiconductor light emitting device detailed above for claim 1, the reference further discloses that the first electrode (EL3 of CT3/ EL3) is further disposed on the passivation layer (IDL of IDL/PRT) disposed on the side surface of the light emitting layer (LE1, LE2, and/or LE3).
Referring to claim 5, for the semiconductor light emitting device detailed above for claim 1, the reference further discloses that the protective layer (PVT) has a shape corresponding to a shape of the first electrode (EL3 of CT3/ EL3) in a sectional view of the semiconductor light emitting device.
Referring to claim 6, the reference further discloses that the protective layer (PVT) is disposed on the passivation layer (IDL of IDL/PRT) disposed on the side surface of the light emitting layer (LE1, LE2, and/or LE3).
Referring to claim 7, for the semiconductor light emitting device detailed above for claim 1, the reference further discloses that the protective layer (PVT) is disposed on the first electrode (EL3 of CT3/ EL3) disposed on the side surface of the light emitting layer.
Referring to claim 10, the reference further discloses that the protective layer (PVT) comprises an insulator (such as SiNx, para [99]).
Referring to claim 12 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses a display device, comprising:
a backplane substrate (PRT/SUB) having a plurality of assembly holes (defined by PVT) corresponding to a plurality of sub-pixels constituting a pixel (comprising LE1, LE2, and/or LE3);
a plurality of semiconductor light emitting devices (LED, Figs. 1A-1C, comprising LE1, LE2, and/or LE3, Figs. 2A-2C) in the plurality of assembly holes, respectively; and
a plurality of first electrode wirings (horizontal portion of EL3, Fig. 2B) on upper sides of the plurality of semiconductor light emitting devices, respectively,
wherein a second inner angle between an inner side surface and a bottom surface of each of the plurality of assembly holes has an obtuse angle (clearly depicted in Figs. 2A-2C), and
wherein the plurality of semiconductor light emitting devices (LED, LE1, LE2, and/or LE3) have shapes corresponding to shapes of the plurality of assembly holes, respectively.
Referring to claim 13 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference further discloses that each of the plurality of semiconductor light emitting devices comprises:
a light emitting layer (LE1, LE2, and/or LE3);
a passivation layer (IDL or IDL /PRT) on an upper surface and a side surface of the light emitting layer;
a protective layer (PVT) on a lower surface and the side surface of the light emitting layer;
a first electrode (CT3/vertical portion of EL3) between the light emitting layer (LE1, LE2, and/or LE3) and the protective layer (PVT); and
a second electrode (108 or CT1) between the light emitting layer (LE1, LE2, and/or LE3) and the passivation layer (IDL or IDL /PRT),
wherein the plurality of semiconductor light emitting devices emit different color lights (para [64], particularly “the colors may be variously changed…”).
Referring to claim 17, for the display device detailed above for claim 12, the reference further discloses a plurality of second electrode wiring (horizontal portion of EL1, Fig. 2B, para [72]) on the upper sides of the plurality of semiconductor light emitting devices.
Referring to claim 18, for the display device detailed above for claim 12, the reference further discloses a plurality of connection electrodes (vertical portions of EL3’s) on side portions of the plurality of semiconductor light emitting devices (LE1, LE2, and/or LE3).
Referring to claim 19 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses a semiconductor light emitting device, comprising:
a light emitting layer (LE1, LE2, and/or LE3) having a first surface, a second surface opposite the first surface, and a lateral surface connecting the first surface and the second surface;
a passivation layer (IDL or IDL /PRT) on the first surface and the lateral surface of the light emitting layer;
a first electrode (CT3 and lower horizontal portion of EL3) extending from the second surface to the lateral surface of the light emitting layer, and without extending to the first surface of the light emitting layer; and
a protective layer (PVT) on the first electrode (CT3/ lower horizontal portion of EL3) and at the first surface of the light emitting layer.
Alternately, referring to claim 19 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses a semiconductor light emitting device, comprising:
a light emitting layer (LE1, LE2, and/or LE3) having a first surface, a second surface opposite the first surface, and a lateral surface connecting the first surface and the second surface;
a passivation layer (PVT) on the first surface and the lateral surface of the light emitting layer;
a first electrode (108, 208) extending from the second surface to the lateral surface of the light emitting layer, and without extending to the first surface of the light emitting layer; and
a protective layer (IDL or IDL /PRT) on the first electrode (108) and at the first surface of the light emitting layer.
Referring to claim 20, the reference further discloses that the protective layer (IDL or IDL /PRT) exposes the first electrode (108, 208) at the lateral surface of the light emitting layer (LE1, LE2, and/or LE3) (for common contact CCT1 (para [72]) to make contact with the first electrode (108, 208) at the lateral surface of the light emitting layer).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 11 and 14-16 are rejected under 35 U.S.C. §103 as being unpatentable over Lee et al. U.S. Patent Application Publication 2020/0144233 A1 (the ‘233 reference).
Referring to claim 11, although the reference does not specifically disclose relative dimensions as claimed, the claimed relative dimensions (“wherein the protective layer has a thickness of 1/10 or less of a thickness of the passivation layer”) will not support the patentability of subject matter encompassed by the prior art (the ‘233 reference discloses that the protective layer (PVT) has a certain thickness and the passivation layer (IDL/PRT) has another thickness) unless there is evidence indicating such relative dimensions are critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation"; MPEP 2144.05.
Referring to claim 14, the reference discloses the display device as detailed above for claim 13 and further discloses that a first inner angle between the side surface and the lower surface of the light emitting layer (LE1, LE2, and/or LE3) of each of the plurality of semiconductor light emitting devices has an obtuse angle (see Fig. 2B). Although the reference does not specifically disclose dimensions as claimed, the claimed dimensions (“wherein the second inner angle is within ±10° with respect to the first inner angle”) will not support the patentability of subject matter encompassed by the prior art (the ‘233 reference discloses that “variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected”, para [52]) unless there is evidence indicating such dimensions are critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation"; MPEP 2144.05.
Referring to claim 15, the reference further discloses that each of the plurality of assembly holes has a minimum diameter at a lower side thereof and a maximum diameter at an upper side thereof. In a same manner as detailed above for claim 14, although the reference does not specifically disclose dimensions as claimed, the claimed dimensions (“wherein at least one of the minimum diameter or the maximum diameter is different in the plurality of assembly holes”) will not support the patentability of subject matter encompassed by the prior art (the ‘233 reference discloses that “variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected”, para [52]) unless there is evidence indicating such dimensions are critical.
Referring to claim 16, in a same manner as detailed above for claim 14, although the reference does not specifically disclose dimensions as claimed, the claimed dimensions (“wherein the second inner angle of the plurality of assembly holes is the same or different”) will not support the patentability of subject matter encompassed by the prior art (the ‘233 reference discloses that “variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected”, para [52]) unless there is evidence indicating such dimensions are critical.
Allowable Subject Matter
5. Claims 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a semiconductor light emitting device with all exclusive limitations as recited in claims 8 and 9, which may be characterized (claim 8) in that an end of the first electrode disposed on the side surface of the light emitting layer is coplanar with an upper surface of the passivation layer, and (claim 9) in that an end of the protective layer disposed on the side surface of the light emitting layer is coplanar with an upper surface of the passivation layer.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
02-04-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818