DETAILED ACTION
Response to Amendment
Amendment filed on 26 May 2026 has been entered. Claims 1-10 are now pending in the application.
Amendments to the claim 4 to overcome the informalities are acceptable. Therefore, claim objections have been withdrawn.
Response to Arguments
Applicant’s arguments, see page 5, filed 26 May 2026, with respect to the rejection(s) of claim(s) 1 and 3 under 35 USC § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ko (US 10952313).
Claim Objections
Claims 1 and 6-7 are objected to because of the following informalities:
In claim 1, line 10: “the intermediate substrate layer” should read:
-- an intermediate substrate layer --
Claim 1, lines 16-17 and claim 6, line 19: “a time domain reflectivity impedance calculation of the via;” should read
-- a time domain reflectivity impedance graph of the via; --
In claim 7, lines 1-3: “wherein forming the intermediate substrate layer includes forming the intermediate substrate layer with the non-functional pad one or more substrate layers from the first pad on the first substrate layer.” should read:
-- wherein forming the intermediate substrate layer includes forming the intermediate substrate layer with the non-functional pads on one or more substrate layers. --
(Please see the 01/19/2026 original claim 7 and 05/26/2026 amended claim 7).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 6-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Noujeim (US 20230319985) in view of Ko (US 10952313).
[AltContent: textbox (non-functional pad)][AltContent: arrow][AltContent: textbox (first pad structure)][AltContent: textbox (top pad)][AltContent: ][AltContent: arrow][AltContent: textbox (second pad structure)][AltContent: ]
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Annotated Fig. 1, Noujeim.
Regarding claim 1, Noujeim teaches, a method of manufacture of an electronic system (manufacturing printed circuit board 100, Figs. 1 to 5) comprising:
forming a first pad structure (see annotated Fig. 1 above) on a first substrate layer (dielectric layer 105) of a mounting substrate (see Fig. 1), the first pad structure having a first pad (loading pad 153b, the loading pads 153a-e may be integrated with the structure of via 154.…are formed from the conductive features 151, which are copper foils, para. [0021-0024]) located within a first anti-pad opening (anti-pad 155b) of a first conductive portion of the first substrate layer (the anti-pads 155a-e may include nonconductive materials, such as insulating materials, to electrically insulate the loading pads 153 from other portions of PCB 100…the anti-pads 155a-e can be defined by a respective void, para. [0026-0027]);
forming a second pad structure (see annotated Fig. 1) on a second substrate layer (dielectric layer 103) of the mounting substrate, the second substrate layer over the first substrate layer (see the dielectric layers 103 and 105, Fig. 1), the second pad structure having a second pad (loading pad 153a, Fig. 1) within a second anti-pad opening (anti-pad 155a, Fig. 1) of a second conductive portion of the second substrate layer (see para. [0021-0024]), and the second substrate layer offset from the first substrate layer by a first offset distance (see plane 164, interface between the top surface of one dielectric layer and the bottom surface of an adjacent dielectric layer may form a plane, such as planes 164, 166, 168, 170, 172, 174, 180, 182, 184, 186, para. [0019], the first loading pad 153b is at an offset distance from the second loading pad 153a, which meets the requirement of the second substrate layer offset from the first substrate layer by a first offset distance);
forming a non-functional pad (loading pads 165a, 165b) on [[the]] an intermediate substrate layer (loading pads 165a-d may be formed on planes between adjacent dielectric layers 102-112, para. [0023]) directly between the first pad and the second pad (see annotated Fig. 1);
forming a via (signal via 154) at least between the first pad and the second pad (see the signal via 154), the via having a conductive portion for electrically coupling the first pad and the second pad (the signal via 154 may be formed through the loading pads 153a-e, para. [0029]), and the first offset distance configured to reduce the level of via impedance between the first pad and the second pad (loading pads extending around the signal via may reduce impedance discontinuity and thus reduce the likelihood of signal distortion, para. [0017]), the via electrically coupled to the non-functional pad (the dimensions, materials, and the configurations of the loading pads 165a-d may be configured to be similar or the same as the loading pads 153a-e, just with different locations where they are formed… loading pads 153a-e,165a-d formed around the signal via 154, para. [0030-0031], in which it is obvious that the non-functional pads 165a and 165b are electrically coupled to the via 154);
forming a top pad (see annotated Fig. 1) on a top substrate layer (dielectric layer 102) over the second substrate layer, the top pad electrically coupled to the via (loading pads 153a-e may be integrated with the structure of via 154…via 154 may be filled with conductive material 161, such as copper, see the signal via 154, Fig. 1, para. [0023-0024]).
[AltContent: textbox (TDR of via including an intermediate conductor)][AltContent: arrow][AltContent: textbox (TDR of conventional via)][AltContent: arrow]
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Annotated Figs. 10 and 11, Ko.
Noujiem does not teach, the first offset distance corresponding to a location of a peak in a time domain reflectivity impedance calculation of the via. However, Ko teaches a method of manufacturing of an electronic system including forming a first pad structure having a first pad (308, Fig. 3) on the first substrate layer (L1); forming a second pad second pad structure (314) on a second substrate layer (L3) offset from the first substrate layer by a first offset distance (see Fig. 3); and the first offset distance corresponding to a location of a peak in a time domain reflectivity impedance calculation of the via (see Figs. 10 and 11, a time domain reflectometry (TDR) graph for a conventional via with no intermediate conductors while FIG. 11 is a TDR graph for the electronic circuit 300 of FIG. 3 including a single intermediate conductor 306, col. 8, lines 35-40, in which it is obvious that, the TDR peak changes with additional dielectric layer or offsetting the dielectric layers).
Noujiem teaches in para. [0023], by forming loading pads 165a-d on a plane 180, 182, 184, 186 between dielectric layers that are in direct contact with one another…, impedance may be lowered so as to reduce the likelihood of signal distortion. From the teachings of Ko in Figs. 10 to 12, including TDR graph of a conventional via in Fig. 10, TDR graph of having single intermediate conductor in Fig. 11, and TDR graph having multiple intermediate conductors in Fig. 12, and from col. 3, lines 1-20, second conductor is separated from the first conductor by a plurality of layers, the one or more intermediate conductors are positioned or placed along the via to modify an impedance profile of the via and thereby improve the return loss of the via in a frequency range of interest, one of ordinary skill in the art would have known that, the change of the peak of TDR impedance graph of the via implies the change in impedance due to the change in number of substrate layers. Therefore, in view of the teachings of Ko, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing of an electronic circuit in Fig. 1 of Noujeim and to include a time domain reflectivity impedance measurement as Ko taught in Figs. 10 to 12 so that it enables improving the return loss of the circuit in a frequency range of interest. Moreover, there is no indication in the instant invention that any surprising results were derived, or that any special steps were devised in the pad structures or offsetting the dielectric layer. The time domain reflectivity impedance calculation of the via is known in the art (see the Note below). Such a combination would have been done by one of ordinary skill in the art without any need for experimentation and with reasonable expectations of success.
Note: Quyang et.al., Optimizing the Placement of Non-Functional Pads on Signal Vias Using Multiple Reflection Analysis, IEEE 2022 Int Symp., Electromagnetic compatibility, page 169-174).
Regarding claim 3, Noujeim in view of Ko teaches the recited limitations with respect to claim 1. Noujeim further teaches, the method as claimed in claim 1, wherein forming the first pad structure includes forming the first pad having a circular pad shape (loading pads 153a-e may be configured to circumscribe around via 154…the loading pads 153a-e may be integrated with the structure of via 154, para. [0021, 0024]) and the first anti-pad opening having a circular shape (an anti-pad extending around the loading pad on the metal plane, para. [0017]) with the first pad offset from a closest side of the first anti-pad opening by a pad gap offset distance (see annotated Fig. 1 below).
[AltContent: textbox (first pad structure)][AltContent: textbox (pad gap offset distance)][AltContent: arrow][AltContent: ]
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Annotated Fig. 1, Noujeim.
Regarding claim 6, Noujeim teaches, a method of manufacture of an electronic system (Figs. 1 to 5) comprising:
forming a first pad structure (see annotated Fig. 1 below) on a first substrate layer (dielectric layer 107) of a mounting substrate (see Fig. 1), the first pad structure having a first pad (loading pad 153c, the loading pads 153a-e may be integrated with the structure of via 154.…are formed from the conductive features 151, which are copper foils, para. [0021-0024]) located within a first anti-pad opening (anti-pad 155c) of a first conductive portion of the first substrate layer (the anti-pads 155a-e may include nonconductive materials, such as insulating materials, to electrically insulate the loading pads 153 from other portions of PCB 100, para. [0026]);
[AltContent: textbox (non-functional pad structure)][AltContent: arrow][AltContent: textbox (second pad structure)][AltContent: ][AltContent: textbox (third pad structure )][AltContent: textbox (first pad structure)][AltContent: arrow][AltContent: ][AltContent: textbox (top pad)][AltContent: ]
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Annotated Fig. 1, Noujeim.
forming an intermediate substrate layer (dielectric layer 106+105+104, see annotated Fig. 1 above) over the first substrate layer of the mounting substrate;
forming a second pad structure (see annotated Fig. 1) on a second substrate layer (dielectric layer 103) of the mounting substrate, the second substrate layer over the first substrate layer and the intermediate substrate layer, the second pad structure having a second pad (loading pad 153a, Fig. 1) within a second anti-pad opening (anti-pad 155a, Fig. 1) of a second conductive portion of the second substrate layer, and the second substrate layer offset from the first substrate layer by a first offset distance (see plane 164, interface between the top surface of one dielectric layer and the bottom surface of an adjacent dielectric layer may form a plane, such as planes 164, 166, 168, 170, 172, 174, 180, 182, 184, 186, para. [0019]);
forming a non-functional pad (loading pads 165a, 165b) on the intermediate substrate layer (loading pads 165a-d may be formed on planes between adjacent dielectric layers 102-112, para. [0023]) directly between the first pad and the second pad (see annotated Fig. 1);
forming a via (signal via 154) at least between the first pad and the second pad, the via having a conductive portion for electrically coupling the first pad and the second pad (the signal via 154 may be formed through the loading pads 153a-e, para. [0029]), and the first offset distance configured to reduce the level of via impedance between the first pad and the second pad (loading pads extending around the signal via may reduce impedance discontinuity and thus reduce the likelihood of signal distortion, para. [0017]), the non-functional pad electrically coupled only to the via on the intermediate layer (the dimensions, materials, and the configurations of the loading pads 165a-d may be configured to be similar or the same as the loading pads 153a-e, just with different locations where they are formed… loading pads 153a-e,165a-d formed around the signal via 154, para. [0030-0031], in which it is obvious that the non-functional pads 165a and 165b are electrically couple to the via 154);
forming a top pad (see annotated Fig. 1) on a top substrate layer (dielectric layer 102) over the second substrate layer, the top pad electrically coupled to the via (via 154 may be filled with conductive material 161, such as copper…conductive material 161 may be the same conductive materials utilized to form the loading pads 153a-e, see the signal via 154, Fig. 1); and
attaching an electronic component to the top pad (printed circuit board (PCB) may provide mechanical support for multiple IC dies or chip assemblies mounted onto the PCB, the sizes and dimensions of the loading pad 165a and the signal via 154 may be varied based on the sizes and dimensions of the electronic components mounted and soldered on the PCB for different electrical performance requirements, para. [0003, 0030]).
Noujiem does not teach, the first offset distance corresponding to a location of a peak in a time domain reflectivity impedance calculation of the via. However, Ko teaches a method of manufacturing of an electronic system including forming a first pad structure having a first pad (308, Fig. 3) on the first substrate layer (L1); forming a second pad second pad structure (314) on a second substrate layer (L3) offset from the first substrate layer by a first offset distance; and the first offset distance corresponding to a location of a peak in a time domain reflectivity impedance calculation of the via (see Figs. 10 and 11, a time domain reflectometry (TDR) graph for a conventional via with no intermediate conductors while FIG. 11 is a TDR graph for the electronic circuit 300 of FIG. 3 including a single intermediate conductor 306, col. 8, lines 35-40).
Noujiem teaches in para. [0023], by forming loading pads 165a-d on a plane 180, 182, 184, 186 between dielectric layers that are in direct contact with one another…, impedance may be lowered so as to reduce the likelihood of signal distortion. Form the teachings of Ko in Figs. 10 to 12, including TDR graph of a conventional via in Fig. 10, TDR graph of having single intermediate conductor in Fig. 11, and TDR graph having multiple intermediate conductors in Fig. 12, and from col. 3, lines 1-20, second conductor is separated from the first conductor by a plurality of layers, the one or more intermediate conductors are positioned or placed along the via to modify an impedance profile of the via and thereby improve the return loss of the via in a frequency range of interest, one of ordinary skill in the art would have known that, the change of the peak of TDR impedance graph of the via implies the change in impedance due to the change in number of substrate layers. Therefore, in view of the teachings of Ko, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing of an electronic circuit in Fig. 1 of Noujeim and to include a time domain reflectivity impedance measurement as Ko taught in Figs. 10 to 12 so that it enables improving the return loss of the circuit in a frequency range of interest. Moreover, there is no indication in the instant invention that any surprising results were derived, or that any special steps were devised in time domain reflectivity impedance calculation, which is known in the art (see the Note above). Such a combination would have been done by one of ordinary skill in the art without any need for experimentation and with reasonable expectations of success.
Regarding claim 7, Noujeim in view of Ko teaches the recited limitations with respect to claim 6. Noujeim further teaches, the method as claimed in claim 6, wherein forming the intermediate substrate layer includes forming the intermediate substrate layer with the non-functional pads (see pad 165a, 165b, Fig. 1) one or more substrate layers from the first pad on the first substate layer.
Regarding claim 8, Noujeim in view of Ko teaches the recited limitations with respect to claim 6. Noujeim further teaches, the method as claimed in claim 6, wherein forming the intermediate substrate layer includes forming the intermediate substrate layer with a third pad structure (see annotated Fig. 1 above) having a third pad (loading pad 153b) and a third anti-pad opening (anti-pad 155b).
Regarding claim 10, Noujeim in view of Ko teaches the recited limitations with respect to claim 6. Noujeim further teaches, the method as claimed in claim 6, wherein forming the intermediate substrate layer includes forming the intermediate substrate layer with a third pad structure (see annotated Fig. 1) having a third pad (loading pad 153b) and a third anti-pad opening (anti-pad 155b), and the via (via 154) electrically coupled to the third pad (the signal via 154 may be formed through the loading pads 153a-e, para. [0029]).
Claim(s) 2, 4-5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Noujeim in view of Ko as applied to claims 1 and 6 above, and further in view of Lin (US 20210022240).
Regarding claim 2, Noujeim further teaches, the method as claimed in claim 1, wherein forming the first pad structure includes forming the first pad (loading pad 153b) having a circular pad shape (loading pads 153a-e may be configured to circumscribe around via 154…the loading pads 153a-e may be integrated with the structure of via 154, para. [0021, 0024]) with the first pad offset from a closest side of the first anti-pad opening by a pad gap offset distance (see annotated Fig. 1 above).
Modified Noujeim does not teach, the first anti-pad opening having a rectangular shape. However, Lin teaches a printed circuit board including forming a first pad structure on a first substrate layer in Fig. 5, the first pad structure having a first pad 136 located within a first anti-pad opening 130 of a first conductive portion of the first substrate layer 160, and forming a via 128 in which,
the method as claimed in claim 1, wherein forming the first pad structure includes forming the first pad (signal pad 136, Fig. 2) having a circular pad shape (see Fig. 2) and the first anti-pad opening (anti-pad 130, Figs. 2 and 3) having a rectangular shape (anti-pad 130 may have a rectangular cross-section, para. [0022]) with the first pad offset from a closest side of the first anti-pad opening by a pad gap offset distance (see Fig. 3). Therefore, in view of the teachings of Lin, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the printed circuit board of Noujeim and replace the circular ani-pad 155b of Noujeim in Fig. 1 with a rectangular anti-pad 130 as taught by Lin in Figs. 2 and 3 so that it enables to optimize the width of the signal lines and to control the impedance of the circuit lines as Lin disclosed in para. [0002].
Regarding claim 4, Noujeim further teaches, the method as claimed in claim 1, wherein forming the first pad structure includes forming the second pad structure (second pad 153 and the second anti-pad 155a, see annotated Fig. 1). Modified Noujeim does not teach, the second pad structure having the second anti-pad shape different from the first anti-pad shape. However, Lin further teaches, second pad structure having the second anti-pad shape different from the first anti-pad shape (anti-pad 130 may have a rectangular cross-section, para. [0022]). Therefore, in view of the teachings of Lin, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the printed circuit board of Noujeim and replace the circular ani-pad 155a of Noujeim in Fig. 1 with a rectangular anti-pad 130 as taught by Lin in Figs. 2 and 3 so that it enables to optimize the width of the signal lines and to control the impedance of the circuit lines.
Regarding claim 5, Noujeim in view of Ko teaches the recited limitations with respect to claim 1. Modified Noujeim does not teach, a second via within the first anti-pad opening. However, Lin further teaches, the method as claimed in claim 1, further comprising forming a second via within the first anti-pad opening (multiple signal vias 124 may be provided within a corresponding anti-pad 130, para. [0016]). Therefore, in view of the teachings of Lin, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the printed circuit board of Noujeim and to include a second via within the anti-pad opening as taught by Lin in Figs. 2 and 3 so that it enables forming multiple signal lines within an anti-pad opening.
Regarding claim 9, Noujeim in view of Ko teaches the recited limitations with respect to claim 6. Noujeim further teaches, the method as claimed in claim 6, wherein forming the intermediate substrate layer includes forming the intermediate substrate layer with a third pad structure (see annotated Fig. 1) having a third pad (loading pad 153b) and a third anti-pad opening (anti-pad 155b).
Modified Noujeim does not teach, a third anti-pad shape different from the first anti-pad opening. However, Lin further teaches, a third anti-pad shape different from the first anti-pad opening (anti-pad 130 may have a rectangular cross-section, para. [0022]) with the first pad offset from a closest side of the first anti-pad opening by a pad gap offset distance (see Fig. 3). Therefore, in view of the teachings of Lin, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the printed circuit board of Noujeim and replace the circular ani-pad 155b of Noujeim in Fig. 1 with a rectangular anti-pad 130 as taught by Lin in Figs. 2 and 3 so that it enables to optimize the width of the signal lines and to control the impedance of the circuit lines.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSE K ABRAHAM/Examiner, Art Unit 3729
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