DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I, claims 1-10 in the reply filed on 19 January 2026 is acknowledged.
Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Objections
Claim 4 is objected to because of the following informalities:
In claim 4, lines 1-2: “wherein forming the first pad structure includes forming the second pad structure” should read:
-- wherein forming the second pad structure includes forming the second pad structure --
See, claim 1 recites, “forming a first pad structure…the first pad structure having a first pad” (emphasis added.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noujeim (US 20230319985).
[AltContent: textbox (first pad structure)][AltContent: textbox (top pad)][AltContent: ][AltContent: arrow][AltContent: textbox (second pad structure)][AltContent: ]
PNG
media_image1.png
396
622
media_image1.png
Greyscale
Annotated Fig. 1, Noujeim.
Regarding claim 1, Noujeim teaches, a method of manufacture of an electronic system (manufacturing printed circuit board 100, Figs. 1 to 5) comprising:
forming a first pad structure (see annotated Fig. 1 above) on a first substrate layer (dielectric layer 105) of a mounting substrate (see Fig. 1), the first pad structure having a first pad (loading pad 153b, the loading pads 153a-e may be integrated with the structure of via 154.…are formed from the conductive features 151, which are copper foils, para. [0021-0024]) located within a first anti-pad opening (anti-pad 155b) of a first conductive portion of the first substrate layer (the anti-pads 155a-e may include nonconductive materials, such as insulating materials, to electrically insulate the loading pads 153 from other portions of PCB 100…the anti-pads 155a-e can be defined by a respective void, para. [0026-0027]);
forming a second pad structure (see annotated Fig. 1) on a second substrate layer (dielectric layer 103) of the mounting substrate, the second substrate layer over the first substrate layer (see the dielectric layers 103 and 105, Fig. 1), the second pad structure having a second pad (loading pad 153a, Fig. 1) within a second anti-pad opening (anti-pad 155a, Fig. 1) of a second conductive portion of the second substrate layer (see para. [0021-0024]), and the second substrate layer offset from the first substrate layer by a first offset distance (see plane 164, interface between the top surface of one dielectric layer and the bottom surface of an adjacent dielectric layer may form a plane, such as planes 164, 166, 168, 170, 172, 174, 180, 182, 184, 186, para. [0019], the first loading pad 153b is at an offset distance from the second loading pad 153a, which meets the requirement of the second substrate layer offset from the first substrate layer by a first offset distance);
forming a via (signal via 154) at least between the first pad and the second pad (see the signal via 154), the via having a conductive portion for electrically coupling the first pad and the second pad (the signal via 154 may be formed through the loading pads 153a-e, para. [0029]), and the first offset distance configured to reduce the level of via impedance between the first pad and the second pad (loading pads extending around the signal via may reduce impedance discontinuity and thus reduce the likelihood of signal distortion, para. [0017]); and
forming a top pad (see annotated Fig. 1) on a top substrate layer (dielectric layer 102) over the second substrate layer, the top pad electrically coupled to the via (loading pads 153a-e may be integrated with the structure of via 154…via 154 may be filled with conductive material 161, such as copper, see the signal via 154, Fig. 1, para. [0023-0024]).
Regarding claim 3, Noujeim teaches the recited limitations with respect to claim 1. Noujeim further teaches, the method as claimed in claim 1, wherein forming the first pad structure includes forming the first pad having a circular pad shape (loading pads 153a-e may be configured to circumscribe around via 154…the loading pads 153a-e may be integrated with the structure of via 154, para. [0021, 0024]) and the first anti-pad opening having a circular shape (an anti-pad extending around the loading pad on the metal plane, para. [0017]) with the first pad offset from a closest side of the first anti-pad opening by a pad gap offset distance (see annotated Fig. 1 below).
[AltContent: textbox (first pad structure)][AltContent: textbox (pad gap offset distance)][AltContent: arrow][AltContent: ]
PNG
media_image1.png
396
622
media_image1.png
Greyscale
Annotated Fig. 1, Noujeim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Noujeim.
Regarding claim 6, Noujeim teaches, a method of manufacture of an electronic system (Figs. 1 to 5) comprising:
[AltContent: textbox (second pad structure)][AltContent: ][AltContent: textbox (third pad structure )][AltContent: textbox (first pad structure)][AltContent: arrow][AltContent: ][AltContent: textbox (top pad)][AltContent: ]
PNG
media_image1.png
396
622
media_image1.png
Greyscale
Annotated Fig. 1, Noujeim.
forming a first pad structure (see annotated Fig. 1 above) on a first substrate layer (dielectric layer 107) of a mounting substrate (see Fig. 1), the first pad structure having a first pad (loading pad 153c, the loading pads 153a-e may be integrated with the structure of via 154.…are formed from the conductive features 151, which are copper foils, para. [0021-0024]) located within a first anti-pad opening (anti-pad 155c) of a first conductive portion of the first substrate layer (the anti-pads 155a-e may include nonconductive materials, such as insulating materials, to electrically insulate the loading pads 153 from other portions of PCB 100, para. [0026]);
forming an intermediate substrate layer (dielectric layer 106+105+104, see annotated Fig. 1 above) over the first substrate layer of the mounting substrate;
forming a second pad structure (see annotated Fig. 1) on a second substrate layer (dielectric layer 103) of the mounting substrate, the second substrate layer over the first substrate layer and the intermediate substrate layer, the second pad structure having a second pad (loading pad 153a, Fig. 1) within a second anti-pad opening (anti-pad 155a, Fig. 1) of a second conductive portion of the second substrate layer, and the second substrate layer offset from the first substrate layer by a first offset distance (see plane 164, interface between the top surface of one dielectric layer and the bottom surface of an adjacent dielectric layer may form a plane, such as planes 164, 166, 168, 170, 172, 174, 180, 182, 184, 186, para. [0019]);
forming a via (signal via 154) at least between the first pad and the second pad, the via having a conductive portion for electrically coupling the first pad and the second pad (the signal via 154 may be formed through the loading pads 153a-e, para. [0029]), and the first offset distance configured to reduce the level of via impedance between the first pad and the second pad (loading pads extending around the signal via may reduce impedance discontinuity and thus reduce the likelihood of signal distortion, para. [0017]);
forming a top pad (see annotated Fig. 1) on a top substrate layer (dielectric layer 102) over the second substrate layer, the top pad electrically coupled to the via (via 154 may be filled with conductive material 161, such as copper…conductive material 161 may be the same conductive materials utilized to form the loading pads 153a-e, see the signal via 154, Fig. 1); and
attaching an electronic component to the top pad (printed circuit board (PCB) may provide mechanical support for multiple IC dies or chip assemblies mounted onto the PCB, para. [0003, 0030], see Note the below).
From the teaching of Noujeim Figs. 1 to 5 and para. [0019], one of ordinary skill in the art would have thought that forming one dielectric layer as an intermediate layer would enable to control the offset distance between the first pad structure and the second pad structure. Therefore, in view of the teachings of Noujeim, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the printed circuit board of Noujeim and replace the dielectric layers 106, 105 and 104 of Noujeim in Fig. 1 with one dielectric layer so that it enables to control and optimize the offset distance between the pad structures and the impedance of the circuit lines of the printed circuit board.
Note: Noujeim teaches in para. [0003], “printed circuit board (PCB) may provide mechanical support for multiple IC dies or chip assemblies mounted onto the PCB” and para. [0030], “the sizes and dimensions of the loading pad 165a and the signal via 154 may be varied based on the sizes and dimensions of the electronic components mounted and soldered on the PCB for different electrical performance requirements” in which it is obvious that “attaching an electronic component to the top pad” unless otherwise defined.
Regarding claim 7, Noujeim teaches the recited limitations with respect to claim 6. Noujeim further teaches, the method as claimed in claim 6, wherein forming the intermediate substrate layer includes forming the intermediate substrate layer with a non-functional pad (see pad 165a, 165b, Fig. 1) directly between the first pad (pad 153b) and the second pad (pad 153a).
Regarding claim 8, Noujeim teaches the recited limitations with respect to claim 6. Noujeim further teaches, the method as claimed in claim 6, wherein forming the intermediate substrate layer includes forming the intermediate substrate layer with a third pad structure (see annotated Fig. 1 above) having a third pad (loading pad 153b) and a third anti-pad opening (anti-pad 155b).
Regarding claim 10, Noujeim teaches the recited limitations with respect to claim 6. Noujeim further teaches, the method as claimed in claim 6, wherein forming the intermediate substrate layer includes forming the intermediate substrate layer with a third pad structure (see annotated Fig. 1) having a third pad (loading pad 153b) and a third anti-pad opening (anti-pad 155b), and the via (via 154) electrically coupled to the third pad (the signal via 154 may be formed through the loading pads 153a-e, para. [0029]).
Claim(s) 2, 4-5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Noujeim as applied to claims 1 and 6 above, and further in view of Lin (US 20210022240).
Regarding claim 2, Noujeim further teaches, the method as claimed in claim 1, wherein forming the first pad structure includes forming the first pad (loading pad 153b) having a circular pad shape (loading pads 153a-e may be configured to circumscribe around via 154…the loading pads 153a-e may be integrated with the structure of via 154, para. [0021, 0024]) with the first pad offset from a closest side of the first anti-pad opening by a pad gap offset distance (see annotated Fig. 1 above).
Noujeim does not teach, the first anti-pad opening having a rectangular shape. However, Lin teaches a printed circuit board including forming a first pad structure on a first substrate layer in Fig. 5, the first pad structure having a first pad 136 located within a first anti-pad opening 130 of a first conductive portion of the first substrate layer 160, and forming a via 128 in which,
the method as claimed in claim 1, wherein forming the first pad structure includes forming the first pad (signal pad 136, Fig. 2) having a circular pad shape (see Fig. 2) and the first anti-pad opening (anti-pad 130, Figs. 2 and 3) having a rectangular shape (anti-pad 130 may have a rectangular cross-section, para. [0022]) with the first pad offset from a closest side of the first anti-pad opening by a pad gap offset distance (see Fig. 3). Therefore, in view of the teachings of Lin, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the printed circuit board of Noujeim and replace the circular ani-pad 155b of Noujeim in Fig. 1 with a rectangular anti-pad 130 as taught by Lin in Figs. 2 and 3 so that it enables to optimize the width of the signal lines and to control the impedance of the circuit lines as Lin disclosed in para. [0002].
Regarding claim 4, Noujeim further teaches, the method as claimed in claim 1, wherein forming the first pad structure includes forming the second pad structure (second pad 153 and the second anti-pad 155a, see annotated Fig. 1). Noujeim does not teach, the second pad structure having the second anti-pad shape different from the first anti-pad shape. However, Lin further teaches, second pad structure having the second anti-pad shape different from the first anti-pad shape (anti-pad 130 may have a rectangular cross-section, para. [0022]). Therefore, in view of the teachings of Lin, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the printed circuit board of Noujeim and replace the circular ani-pad 155a of Noujeim in Fig. 1 with a rectangular anti-pad 130 as taught by Lin in Figs. 2 and 3 so that it enables to optimize the width of the signal lines and to control the impedance of the circuit lines.
Regarding claim 5, Noujeim teaches the recited limitations with respect to claim 1. However, Noujeim does not teach, a second via within the first anti-pad opening. However, Lin further teaches, the method as claimed in claim 1, further comprising forming a second via within the first anti-pad opening (multiple signal vias 124 may be provided within a corresponding anti-pad 130, para. [0016]). Therefore, in view of the teachings of Lin, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the printed circuit board of Noujeim and to include a second via within the anti-pad opening as taught by Lin in Figs. 2 and 3 so that it enables forming multiple signal lines within an anti-pad opening.
Regarding claim 9, Noujeim teaches the recited limitations with respect to claim 6. Noujeim further teaches, the method as claimed in claim 6, wherein forming the intermediate substrate layer includes forming the intermediate substrate layer with a third pad structure (see annotated Fig. 1) having a third pad (loading pad 153b) and a third anti-pad opening (anti-pad 155b).
Noujeim does not teach, a third anti-pad shape different from the first anti-pad opening. However, Lin further teaches, a third anti-pad shape different from the first anti-pad opening (anti-pad 130 may have a rectangular cross-section, para. [0022]) with the first pad offset from a closest side of the first anti-pad opening by a pad gap offset distance (see Fig. 3). Therefore, in view of the teachings of Lin, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the printed circuit board of Noujeim and replace the circular ani-pad 155b of Noujeim in Fig. 1 with a rectangular anti-pad 130 as taught by Lin in Figs. 2 and 3 so that it enables to optimize the width of the signal lines and to control the impedance of the circuit lines.
Conclusion
Prior art Fukuchi (US 20160128191) teaches a method of manufacture of an electronic system comprising: forming a first pad structure on a first substrate layer, the first pad structure having a first pad located within a first anti-pad opening of a first conductive portion of the first substrate layer; forming a second pad structure on a second substrate layer, the second substrate layer over the first substrate layer, the second pad structure having a second pad within a second anti-pad opening of a second conductive portion of the second substrate layer, and the second substrate layer offset from the first substrate layer by a first offset distance; forming a via; and forming a top pad on a top substrate layer.
Prior art Mutnury (US 20110267783) teaches a circuit board including a first pad structure having a first pad located within a first anti-pad opening; forming a second pad structure on a second substrate layer, the second pad structure having a second pad within a second anti-pad opening, and the second substrate layer offset from the first substrate layer by a first offset distance; forming a via; and forming a top pad on a top substrate layer.
Prior art Twardy (US 20100314163) teaches a circuit board including a first pad structure having a first pad located within a first anti-pad opening; forming a second pad structure on a second substrate layer, the second pad structure having a second pad within a second anti-pad opening, and the second substrate layer offset from the first substrate layer by a first offset distance; forming a via; and forming a top pad on a top substrate layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THOMAS J. HONG can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSE K ABRAHAM/Examiner, Art Unit 3729 /THOMAS J HONG/Supervisory Patent Examiner, Art Unit 3729