DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's election with traverse of Species I in Figure 1 corresponding to original claims 1-12 and 14-15 in the reply filed on 03/03/26 is acknowledged. However, Species II in Figure 14 for claims 13 and 16 to read non- elected species. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement. Therefore, the restriction requirement is still deemed proper and is therefore made FINAL.
By this election, claims 13 and 16 are withdrawn and claims 1-16 are pending in the application.
The office action of the examination of claims 1-12 and 14-15 is set forth below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8-9, 12 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wong et al. “Vertical ß -Ga2O3 Power Transistors: A Review”, Vol. 57, No. 10, 2020, pages 3925-3937 as disclosed by the applicant's IDS filed 07/22/25 in view of Hitora et al. (US 2015/0325660 A1).
Regarding claims 1-2, Wong (Figs. 2 and 9) discloses a semiconductor device comprising at least: a crystalline oxide semiconductor layer including a Si+-implanted channel layer and a Ga₂O₃ drift layer (see Fig. 2, page 3927 and page 3929); and a gate electrode G arranged over the channel layer across a gate insulating film Al₂O₃, and having a current blocking layer (CBL) between the channel layer and the drift layer, the drift layer Ga₂O₃ containing a first crystalline oxide as a major component, the current blocking layer (CBL) containing a second crystalline oxide as a major component (Mg++ implant), the first crystalline oxide and the second crystalline oxide having different compositions (see Fig. 2 and page 3927).
Wong discloses all the claimed limitations of the invention but Wong does not expressly disclose the oxide semiconductor layer being crystalline.
However, Hitora (Fig. 6) discloses a semiconductor device comprising an oxide semiconductor layer 19. In paragraph [0052], Hitora discloses using a material that is crystalline, and may include metal oxides.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device of Wong as taught by Hitora to have the oxide semiconductor layer being crystalline in order to have an ordered structure with minimal defects that provides better electrical performance and stability (Fig. 6, [0052]).
Regarding claim 3, as discussed, the combination above, Hitora (Fig. 6) discloses wherein the first crystalline oxide has a corundum structure ([0052]).
Regarding claims 4-5, as discussed, the combination above, Hitora (Fig. 6) discloses wherein the second crystalline oxide 22 (InAlGaO) is a mixed crystal containing at least one type of metal selected from Group 6 to Group 10 of the periodic table and at least a metal in Group 13 of the periodic table ([0056]).
Regarding claim 6, Wong does not expressly disclose wherein the second crystalline oxide is a mixed crystal containing at least a metal in Group 9 of the periodic table and a metal in Group 13 of the periodic table. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416. Accordingly, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the device of Wong by forming the second crystalline oxide is a mixed crystal containing at least a metal in Group 9 of the periodic table and a metal in Group 13 of the periodic table, because such a forming the different material can vary depending upon the device in a particular application.
Regarding claim 8, as discussed, the combination above, Hitora (Fig. 18) discloses wherein the current blocking layer 132 has a p-type conductivity type ([0125]).
Regarding claim 9, Wong (Figs. 2 and 9) discloses comprising: a source region S provided in at least a part of the channel layer and a source electrode (PAD) provided on the source region.
Regarding claim 12, Wong (Figs. 2 and 9) discloses wherein the semiconductor device is a transistor.
Regarding claims 14-15, Wong in view of Hitora does not disclose a power converter or control system. However, it would have been obvious to one of ordinary skill in the art to have the semiconductor device in a power converter or control system in order to utilize the semiconductor device in more robust electronic devices according to the preferences of the user.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wong et al. “Vertical ß -Ga2O3 Power Transistors: A Review”, Vol. 57, No. 10, 2020, pages 3925-3937 as disclosed by the applicant's IDS filed 07/22/25 in view of Hitora et al. (US 2015/0325660 A1) and further in view of Yamazaki et al. (US 2016/0190333 A1).
Regarding claim 7, Wong in view of Hitora does not expressly disclose the second crystalline oxide has a bandgap equal to or greater than 3.0 eV.
However, Yamazaki (Fig. 1B) discloses the second crystalline oxide has a bandgap equal to or greater than 3.0 eV (see paragraph [0226]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device of Wong as taught by Yamazaki to have the second crystalline oxide has a bandgap equal to or greater than 3.0 eV, because such a forming the band gap can be varied for other implementations.
Allowable Subject Matter
Claims 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fails to disclose all the limitations recited in the above claims. Specifically, the prior art of record fails to disclose wherein the source electrode directly contacts the current blocking layer (claim 10); or wherein the crystalline oxide semiconductor layer has a trench penetrating at least the channel layer, and at least a part of the gate electrode is buried in the trench across the gate insulating film (claim 11).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THERESA T DOAN whose telephone number is (571)272-1704. The examiner can normally be reached on Monday, Tuesday, Wednesday and Thursday from 7:00AM - 3:00PM.
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/THERESA T DOAN/ Primary Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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