DETAILED ACTION
This is in response to the request for continued examination filed on 11/17/2025.
Status of Claims
Claims 1 – 14 are pending, of which claims 1 and 8 are in independent form.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/17/2025 has been entered.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jerolm, U.S. Patent Application 2020/0092134 (hereinafter referred to as Jerolm) in view of Matsunaga, U.S. Patent Application 2017/0091130 (hereinafter referred to as Matsunaga), further in view of Arnould, U.S. Patent Application 2020/0409902 (hereinafter referred to as Arnould).
Referring to claim 1, Jerolm discloses “A serial communication bus system” (Fig. 1) “with a dynamic address table” ([0016]-[0017] master maintains a table of communication-ready data bus subscribers and their addresses as well as their relative positions. The mapping is updated when a new data bus subscriber is connected to the bus or when a data bus subscriber is removed) “comprising: a single master device” (Fig. 1 local bus master 3); “multiple slave devices” (Fig. 1 data bus subscribers 7a, 7b, ..., 7n), “where each of said slave devices can be one of a connected device and a newly connected device” ([0016] – [0017] when a new data bus subscriber is connected to the bus or when a data bus subscriber is removed); and “a serial communication bus, serving as a connection interface between said master device and said slave devices” (Fig. 1 and [0055] bus master 3 interface connects to the local bus and the data subscribers. The local bus may alternatively be designed to be stranded or star-shaped, or to have a combination or mixture of the above designs); “wherein said master device has a dynamic address table with multiple bits” ([0016]-[0017] master maintains a table of communication-ready data bus subscribers and their addresses as well as their relative positions).
Jerolm does not appear to explicitly disclose “a dynamic address table with multiple bits, each corresponding to said slave devices, and if said slave device is said connected device, the corresponding bit has a first logic state; if said slave device is said newly connected device, before connection, the corresponding bit has a second logic state, and after connection, said master device assigns a simulated identification code to said newly connected device as a device address, and upon confirmation, updates the bit value of the corresponding bit from said second logic state to said first logic state.”
However, Matsunaga discloses another bus system for connecting master devices to slave devices (Fig. 1) and teaches “a dynamic” “table with multiple bits, each corresponding to said slave devices, and if said slave device is said connected device, the corresponding bit has a first logic state; if said slave device is said newly connected device, before connection, the corresponding bit has a second logic state” (Fig. 4 status register and [0063] a plurality of bit values representing whether n master devices and m slave devices are valid/invalid and whether or not they are in a normal state/failure state. Also [0067] and [0069] validity flag and failure flag, each with a bit corresponding to a slave device, the validity flag means the system includes the device (connected). The validity flag being “1” indicates that bus system 21 includes slave device SLj and “0” indicates that bus system 21 does not include slave device SLj).
As above, Jerolm teaches a master maintains a table of communication-ready data bus subscribers and their addresses as well as their relative positions and the mapping is updated when a new data bus subscriber is connected to the bus or when a data bus subscriber is removed ([0016]-[0017]). Further, Matsunaga teaches a validity flag indicating whether the bus system includes a slave or not ([0067], [0069]).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Matsunaga with Jerolm so that the master “updates the bit value of the corresponding bit from said second logic state to said first logic state” when a new slave device is connected. This would lead to the situation where some slaves have a corresponding ‘1’ in the validity flag (as shown in Fig. 4 and [0067]).
Jerolm and Matsunaga are analogous art because they are from the same field of endeavor, which is master/slave bus methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jerolm and Matsunaga before him or her, to modify the teachings of Jerolm to include the teachings of Matsunaga so that the dynamic table of slave addresses includes bits each corresponding to a slave device, the bits state conveying information on whether the slave is connected or not.
The motivation for doing so would have been to provide a centralized set of data describing the status of the system (as described by Matsunaga at [0061]). Further, utilizing a single bit/flag each corresponding to a slave device saves space.
Neither Jerolm nor Matsunaga appears to explicitly disclose “and after connection, said master device assigns a simulated identification code to said newly connected device as a device address.”
Jerolm teaches “said master device assigns a” new address “ “to said newly connected device as its device address” ([0087] field 26 for assigning a new address to the data subscribers and [0016] – [0017] when a new data bus subscriber is connected to the bus or when a data bus subscriber is removed). Jerolm also discloses “a simulated identification code” ([0085] fields used for identification and interim identification and [0094] counter values used to map data packets to data bus subscribers).
Also, Arnould discloses “and after connection, said master device assigns a simulated identification code to” a slave device “as a device address” (Fig. 2 and [0063] The device 1 is configured so as to replace the default address ADD1 within the slave integrated circuit 2 with a replacement address ADD3 upon receiving an addressing message MESS conveyed on the bus 3 and containing the replacement address ADD3.” “[0064] The master integrated circuit 4 is configured so as to transmit the addressing message MESS.”).
It would have been obvious to one of ordinary skill in the art to combine Arnould’s replacing of addresses with the dynamic system of Jerolm/Matsunaga so that the address that is being replaced belongs to “said newly connected device.”
Finally, as above, it would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Matsunaga with Jerolm so that the master “updates the bit value of the corresponding bit from said second logic state to said first logic state” when a new slave device is connected.
Further, as seen in Arnould, “confirmation takes place after each byte” (Fig. 1 and [0014]).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Arnould with Jerolm and Matsunaga so that the master “upon confirmation, updates the bit value of the corresponding bit from said second logic state to said first logic state.”
This would a means for ensuring that the new slave address has been accepted by the slave.
Jerolm, Matsunaga, and Arnould are analogous art because they are from the same field of endeavor, which is master/slave bus methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jerolm, Matsunaga, and Arnould before him or her, to modify the teachings of Jerolm and Matsunaga to include the teachings of Arnould so that the master assigns an identification code to a newly connected device.
The motivation for doing so would have been to provide a means for configuring slave addresses without complicating the circuit and/or adding ports (as described by Arnould at [0016] – [0021]).
Therefore, it would have been obvious to combine Arnould with Jerolm and Matsunaga to obtain the invention as specified in the instant claim.
As per claim 2, Arnould discloses “said serial communication bus is an Inter-Integrated Circuit (I2C) bus” ([0027] I2C bus).
As per claims 3 and 4, Jerolm discloses “said dynamic address table” ([0016]-[0017] master maintains a table of communication-ready data bus subscribers and their addresses as well as their relative positions. The mapping is updated when a new data bus subscriber is connected to the bus or when a data bus subscriber is removed).
Also, Arnould discloses “a common initial address” and “said common initial address can be a General Call address” ([0036] default address and [0078] general call).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine the teachings of Arnould with the teachings of Jerolm and Matsunaga so that said dynamic address table has a common initial address.
As per claim 5, Jerolm discloses “said dynamic address table” ([0016]-[0017] master maintains a table of communication-ready data bus subscribers and their addresses as well as their relative positions. The mapping is updated when a new data bus subscriber is connected to the bus or when a data bus subscriber is removed).
Neither Jerolm nor Matsunaga nor Arnould appears to explicitly disclose “said dynamic address table has 128 bits.”
However, Matsunaga teaches a table wherein each slave has a corresponding validity bit (Fig. 4 status register and [0063] a plurality of bit values representing whether n master devices and m slave devices are valid/invalid and whether or not they are in a normal state/failure state. Also [0067] and [0069] validity flag and failure flag, each with a bit corresponding to a slave device, the validity flag means the system includes the device (connected). The validity flag being “1” indicates that bus system 21 includes slave device SLj and “0” indicates that bus system 21 does not include slave device SLj).
Further, it is understood by one of ordinary skill in the art that the I2C specification calls for a 7-bit address. This leads to 27 (128) possible connected devices that can be uniquely addressed.
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to create a dynamic address table that includes a corresponding bit for the maximum possible number of uniquely addressable slave devices.
This would provide a means for handling any number of slave devices, up to the maximum possible number of uniquely addressable slave devices.
As per claim 6, Jerolm discloses “a dynamic address table” ([0016]-[0017] master maintains a table of communication-ready data bus subscribers and their addresses as well as their relative positions. The mapping is updated when a new data bus subscriber is connected to the bus or when a data bus subscriber is removed).
Further, Matsunaga discloses “a dynamic” “table” “wherein “said first logic state is logic 1, and said second logic state is logic 0” (Fig. 4 and [0067], [0069] validity flag and failure flag, each with a bit corresponding to a slave device. validity flag set to “1” means the system includes the slave device, validity flag set to “0” means the system does not include the slave device).
As per claim 7, Arnould discloses “the confirmation is achieved through an acknowledgment (ACK) signal” ([0014] ACK after each byte, the confirmation bit ACK allows the receiver to signal to the transmitter that the byte has been successfully received and that another byte may be dispatched).
Referring to claim 8, claim 1 recites the corresponding limitations as that of claim 8. Therefore, the rejection of claim 1 applies to claim 8.
Also, it would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to include “(a) initializing said dynamic address table” and “(d) Returning to step (b).”
Initializing the dynamic address table would include setting the bits/flags to zero before any slave devices are found to be included in the bus system. As taught by Matsunaga validity flag being “1” indicates that bus system 21 includes slave device SLj and “0” indicates that bus system 21 does not include slave device SLj (Fig. 4 along with [0067] and [0069]). Initializing this data would ensure that no previous system status information is present after a system change.
Further, Jerolm discloses “(b) transmitting, by said master device via said serial communication bus, a device address assigned to said connected device” (Fig. 2 old address 25 and new address 26). Further still, Arnould discloses “(b) transmitting, by said master device via said serial communication bus, a device address assigned to said connected device” (Fig. 1 SLADR and Fig. 2 and [0064] MESS message includes default address that was assigned to the connected device).
Also, as above, Jerolm teaches “said master device assigns a” new address “ “to said newly connected device as its device address” ([0087] field 26 for assigning a new address to the data subscribers and [0016] – [0017] when a new data bus subscriber is connected to the bus or when a data bus subscriber is removed). Jerolm also discloses “a simulated identification code” ([0085] fields used for identification and interim identification and [0094] counter values used to map data packets to data bus subscribers).
Further, Arnould discloses “said master device assigns a simulated identification code to” a slave device “as its device address” (Fig. 2 and [0063] The device 1 is configured so as to replace the default address ADD1 within the slave integrated circuit 2 with a replacement address ADD3 upon receiving an addressing message MESS conveyed on the bus 3 and containing the replacement address ADD3.” “[0064] The master integrated circuit 4 is configured so as to transmit the addressing message MESS.”).
It would have been obvious to one of ordinary skill in the art to combine Arnould’s replacing of addresses with the dynamic system of Jerolm/Matsunaga so that the address that is being replaced belongs to “said newly connected device.”
Further, the step of “(d) returning to step (b)” is merely describing duplicating the addressing method for further connected slave devices. It would have been obvious to one of ordinary skill to set addresses to multiple slave devices and to duplicate the address-setting methods of Jerolm, Matsunaga, and Arnould. Also, as learned from In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960), mere duplication of parts has no patentable significance unless a new and unexpected result is produced.
As above, Jerolm, Matsunaga, and Arnould are analogous art because they are from the same field of endeavor, which is master/slave bus methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jerolm, Matsunaga, and Arnould before him or her, to modify the teachings of Jerolm and Matsunaga to include the teachings of Arnould so that the master assigns an identification code to a newly connected device.
The motivation for doing so would have been to provide a means for configuring slave addresses without complicating the circuit and/or adding ports (as described by Arnould at [0016] – [0021]).
Therefore, it would have been obvious to combine Arnould with Jerolm and Matsunaga to obtain the invention as specified in the instant claim.
Note, claim 9 recites the corresponding limitations of claim 2. Therefore, the rejection of claim 2 applies to claim 9.
Note, claim 10 recites the corresponding limitations of claim 3. Therefore, the rejection of claim 3 applies to claim 10.
Note, claim 11 recites the corresponding limitations of claim 4. Therefore, the rejection of claim 4 applies to claim 11.
Note, claim 12 recites the corresponding limitations of claim 5. Therefore, the rejection of claim 5 applies to claim 12.
Note, claim 13 recites the corresponding limitations of claim 6. Therefore, the rejection of claim 6 applies to claim 13.
Note, claim 14 recites the corresponding limitations of claim 7. Therefore, the rejection of claim 7 applies to claim 14.
Response to Arguments
Applicant's arguments filed 11/17/2025 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., removal of devices without disrupting bus connectivity/system operation, non-format-limiting data packets, reassigning/re-using addresses upon reconnection, standard I2C addressing, and the use of SID value with incrementing, etc.) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant argues, on page 8, that Jerolm’s ring bus architecture a) is not a serial bus and b) does not allow removal of a device without disrupting connectivity of the entire bus.
The examiner disagrees. First, Jerolm’s ring bus is considered to be a serial bus. Pavluchenko NPL and M Bus NPL are provided as evidentiary references to show that a ring bus is considered a serial bus in the art. See Pavluchenko at Fig. 2 and M Bus at Fig. 1 and its following description.
Secondly, as above, Applicant’s argument that Jerolm’s system does not allow removal of a device without disrupting connectivity of the entire bus is not claimed. The examiner agrees with Applicant’s description of Jerolm’s bus system in that removal of devices would disrupt bus connectivity/system operation. However, such a feature is not claimed. As in the claim rejections, Jerolm teaches data subscribers being connected and removed ([0017]). Applicant's argument that removal would disrupt the bus connectivity does not negate Jerolm's teachings.
Applicant argues, on page 9, that the claimed subject matter of the present application does not rely on any specific packet structure. Device detection, communication, and management in the present invention do not require the format-limiting data packets mandated by Jerolm.
Again, these features are not claimed. If Applicant can clearly delineate the features of Jerolm’s data packets from the instant application, the examiner recommends adding such a limitation to the claims.
Applicant argues, on page 9, that Matsunaga discloses multiple master and multiple slaves on a bus and states that ”if the claimed subject matter of the present application were applied to multiple masters, it would cause bus disorder.”
The examiner disagrees. One of ordinary skill in the art at the time of Applicant’s filing would understand how to incorporate Matsunaga’s slave states into the single master/multiple slave system of Jerolm.
Applicant argues, on pages 9 – 10, that Arnould “repeatedly discusses the concept of a replacement address and further specifies that the newly assigned address will be retained even after a restart; in contrast, the present invention reassigns the address upon reconnection once a device is removed.”
Again, these features are not claimed. If Applicant can clearly delineate the features of Arnould’s retained addresses from the instant application, the examiner recommends adding such a limitation to the claims.
Applicant argues, on page 10, that Arnould “resolves address conflicts when multiple devices share the same slave address. The present invention, however, concerns a master-side management method that only detects when a slave device is connected or removed, without addressing any address-conflict problems. This indicates another fundamental difference between the two technologies.”
Again, this argument is not directed at any claim language.
Applicant argues, on page 10, that Arnould “communicates with the slave device through special commands and specific data formats, whereas the present invention simply uses standard FC addressing to determine whether a device exists on the bus.”
Again, these features are not claimed. If Applicant can clearly delineate the features of Arnould’s special commands and data formats from the instant application, the examiner recommends adding such a limitation to the claims.
Finally, Applicant argues, on page 10, that while the previous Office Action stated “the SID is not claimed as being specifically incremented as an index used and interpreted as a device address that sits behind the unified and shared I2C bus address common to all the attached and connected slave devices. Instead, Applicant claims “assign[ing] a simulated identification code to said newly connected device as a device address.” Applicant’s claims never mention ‘index’ or ‘increment.’ As below, several teachings in the prior art are considered equivalent to this limitation.
Jerolm teaches an interim identification ([0085]) as well as counters for mapping data packets to appropriate subscribers ([0094]). Further, Arnould teaches a default address that is later replaced with a replacement address (Fig. 2 and [0063]). Both can be considered equivalent to a “simulated identification code” under the broadest reasonable interpretation.
Again, if Applicant can clearly delineate the features of Jerolm’s and Arnould’s identification/address from the instant application, the examiner recommends adding such a limitation to the claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
‘Wired M-Bus Specification - section 2 – The Basics of Serial Bus Systems’ copyright 2020 by M-Bus.
‘Simple and Robust Multipoint Data Acquisition Bus Built on Top of the Standard RS-232 Interface’ by Alexey PAVLUCHENKO et al., May 2016.
U.S. Patent Application 20140149616 teaches an I2C system with an address table including bits for slaves.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184