DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 4, 6 – 8, 11 – 14 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al. (US 2022/0157819).
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(Claim 1) Jung et al. teach a semiconductor memory device, comprising:
a semiconductor substrate (100);
a stack structure (ST1) that includes word lines (WL) and interlayer dielectric patterns (ILD) that are alternately stacked on the semiconductor substrate;
an etch stop layer (TIL, paragraph 41) on the stack structure;
semiconductor patterns (SP) that penetrate the word lines (WL);
a bit line (BL) in contact (figs. 16B, 18B) with the semiconductor patterns (SP);
capping dielectric patterns (CP, paragraph 106) between the bit line and the word lines, the capping dielectric patterns covering sidewalls of the word lines; and
a data storage element (CAP) on the semiconductor substrate,
wherein a level of a bottom surface of the etch stop layer (TIL) is the same as a level of a top surface of the data storage element (CAP).
(Claim 2) Jung et al. teach a level of a top surface of the bit line (BL) is the same as the level of the bottom surface of the etch stop layer (TIL).
(Claim 3) Jung et al. teach wherein the bottom surface of the etch stop layer is in contact with the data storage element.
(Claim 4) Jung et al. teach wherein the bottom surface of the etch stop layer (TIL) is in contact with the bit line (BL).
(Claim 6) wherein (fig. 18A):
the semiconductor patterns (SP) include:
first lateral surfaces (SD1) in contact with the bit line (BL); and
second lateral surfaces (SD2) in contact with the data storage elements (CAP), the data storage element (CAP) includes:
storage electrodes (SE) in contact with the second lateral surfaces (SD2) of the semiconductor patterns (SP) and parallel to a top surface of the semiconductor substrate;
a capacitor dielectric layer (CIL) that conformally covers the storage electrodes; and
a plate electrode (PE) on the capacitor dielectric layer (CIL), and
the bottom surface of the etch stop layer (TIL) is in contact with a top surface of the capacitor dielectric layer (TIL).
(Claim 7) Jung et al. teach wherein the etch stop layer (TIL) includes an oxide (paragraph 41).
(Claim 8) Jung et al. teach the device, further comprising:
a first separation dielectric pattern (ST1) between the bit lines; and
a second separation dielectric pattern (ST2) between the data storage elements,
wherein a level of a top surface of the first separation dielectric pattern (ST1) is the same as the level of the bottom surface of the etch stop layer (TIL).
(Claim 11) Jung et al. teach a semiconductor memory device, comprising:
a semiconductor substrate (100);
a stack structure (ST1) that includes word lines (WL) and interlayer dielectric patterns (ILD) that are alternately stacked on the semiconductor substrate;
an etch stop layer (TIL) on the stack structure;
semiconductor patterns (SP) that penetrate the word lines;
a bit line (BL) in contact with the semiconductor patterns;
capping dielectric patterns (CP) between the bit line (BL) and the word lines (WL), the capping dielectric patterns covering sidewalls of the word lines (WL); and
a data storage element (CAP) on the semiconductor substrate, wherein a level of a bottom surface of the etch stop layer (TIL) is the same as a level of a top surface of the bit line(BL).
(Claim 12) Jung et al. teach wherein the etch stop layer includes SiO2 or SiN (paragraph 41).
(Claim 13) Jung et al. teach wherein the etch stop layer further includes C, N, O, or B (paragraph 41).
(Claim 14) the device, further comprising a peripheral layer on the etch stop layer, wherein:
the etch stop layer (TIL) includes a connection post (PE embedded in TIL), and the stack structure and the peripheral layer are electrically connected through the connection post.
(Claim 18) Jung et al. teach the device, further comprising a vertical dielectric pattern (130) in contact with the bit line (BL), wherein a top surface of the vertical dielectric pattern (130) is coplanar with the bottom surface of the etch stop layer (TIL).
Claims 19 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato et al. (US 2021/0408035).
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(Claim 19) Sato et al. teach a semiconductor memory device, comprising:
a lower substrate;
a peripheral layer (100, 200) on the lower substrate;
a first stack structure (165) that includes word lines (146) and interlayer dielectric patterns (132) that are alternately stacked on the peripheral layer;
a first etch stop layer (180, paragraph 128) on the first stack structure;
a second stack structure (265) that includes word lines (246) and interlayer dielectric patterns (232) that are alternately stacked on the first etch stop layer; and
a second etch stop layer (270, paragraph 146) on the second stack structure,
wherein the first stack structure and the second stack structure are electrically connected (fig. 40A #276, paragraph 291) to each other.
(Claim 20) Sato et al. teach wherein the first etch stop layer (180, doped silicate glass, paragraph 116) and the second etch stop layer (270, silicon oxide, paragraph 136) include different materials from each other.
Allowable Subject Matter
Claims 5, 9, 10, 15 – 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(Claims 5) the bottom surface of the etch stop layer in contact with a top surface of the plate electrode.
(Claim 9) wherein the bottom surface of the etch stop layer is in contact with a top surface of the vertical dielectric pattern.
(Claim 10) wherein the interlayer dielectric patterns include an air gap, and the etch stop layer includes TiN or W.
(Claim 15) a level of a top surface of the plate electrode is the same as the level of the bottom surface of the etch stop layer.
Conclusion
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
April 1, 2026