DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kushner (US 2019/0371924).
With regard to claim 1, Kushner, in Figure 19, discloses a device comprising: a silicon-controlled rectifier (100); at least one first transistor (1901) connected between an anode (103) of the silicon-controlled rectifier and a gate (107) of the silicon-controlled rectifier; and a second transistor (1904), wherein a source of the second transistor is connected to one from among the anode and a cathode (104) of the silicon-controlled rectifier, and wherein a drain of the second transistor is connected to a body of the at least one first transistor (as seen in Fig. 19, both the drain of transistor 1904 and the body of transistor 1901 are coupled to the gate 107 of the SCR 100) (re claim 1), wherein the at least one first transistor and the second transistor each comprise an n-channel field effect transistor (paragraph 0079), and wherein the source of the second transistor is connected to the cathode (104) (re claim 2), wherein a gate of the at least one first transistor is connected to the cathode (through transistor 1904), and wherein a gate of the second transistor is connected to the cathode (as seen in Fig. 19) (re claim 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kushner in view of Sato (US 2005/0212009).
With regard to claim 4, Kushner teaches the device of claim 2, wherein a gate of the at least one first transistor (1901) is connected to the cathode (through transistor 1904).
Kushner does not teach a capacitor connected between the anode and a gate of the second transistor; and a resistor connected between the gate of the second transistor and the cathode.
Sato, in Figure 11, teaches an SCR protection circuit similar to Kushner wherein an SCR (21) is coupled to a first transistor (35-1 & 35-n) and a second transistor (27) coupled similarly to the transistors of Kushner. Sato further teaches a capacitor (30) connected between the anode and a gate of the second transistor (27); and a resistor (31) connected between the gate of the second transistor and the cathode (paragraph 0059).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kushner with Sato, by coupling the gate of the second transistor of Kushner to a timer circuit as taught by Sato, for the purpose of allowing for the safety circuit to be used to protect from fast transient ESD fault conditions while allowing almost no leakage current to flow during normal operation.
With regard to claim 5, Kushner teaches the device of claim 1 and further teaches that the at least one first transistor comprises an n-channel field effect transistor (NFET).
Kushner does not teach that the second transistor comprises a p-channel field effect transistor (PFET), and wherein the source of the second transistor is connected to the anode.
Sato, in Figure 14, teaches an SCR protection circuit similar to Kushner wherein an SCR (21) is coupled to a first transistor (35-1 & 35-n) and a second transistor (29) coupled similarly to the transistors of Kushner. Sato further teaches that the at least one first transistor (35-1 & 35-n) comprises an n-channel field effect transistor (NFET), wherein the second transistor comprises a p-channel field effect transistor (PFET), and wherein the source of the second transistor is connected to the anode (through transistors 35-1 & 35-n).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kushner with Sato, by coupling the gate of the second transistor of Kushner to a timer circuit as taught by Sato, for the purpose of allowing for the safety circuit to be used to protect from fast transient ESD fault conditions while allowing almost no leakage current to flow during normal operation.
With regard to claims 6 & 7, Kushner in view of Sato discloses the device of claim 5, and further discloses that a gate of the at least one first transistor (Kushner, 1901), is connected to the cathode (through transistor 1904), and wherein a gate of the second transistor is connected to the anode (through the resistor 31 of Sato) (re claim 6), further comprising: a resistor (31 of Sato) connected between the anode and a gate of the second transistor; and a capacitor (30 of Sato) connected between the gate of the second transistor and the cathode, wherein a gate of the at least one first transistor (Kushner, 1901) is connected to the cathode (through the resistor 31 of Sato) (re claim 7), wherein the at least one first transistor comprises a plurality of first transistors (Sato, 35-1=35-n) which are serially connected between the anode and the gate of the silicon-controlled rectifier (re claim 8).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kushner.
With regard to claim 9, Kusher discloses the claimed invention except that a channel width of the second transistor is different from a channel width of the at least one first transistor. It would have been obvious to one of ordinary skill in the art at the time the invention was made to set an appropriate channel width for each transistor to ensure that each transistor can operate without damage while not occupying too much space, since it has been held that discovering an optimal value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claim 10 rejected under 35 U.S.C. 103 as being unpatentable over Kushner as applied to claim 1 above, and further in view of Arai (US 7,440,248).
With regard to claim 10, Kushner teaches the device of claim 1.
Kushner does not teach a capacitor connected between the anode and a gate of the at least one first transistor; and a resistor connected between the gate of the at least one first transistor and the cathode.
Arai, in Figure 1, teaches an SCR device similar to Kushner wherein a capacitor (10) is connected between the anode and a gate of the at least one first transistor (8); and a resistor (11) connected between the gate of the at least one first transistor and the cathode. It is further noted that the inverter 9 and PFET 8 is the equivalent of an NFET as taught by Kushner.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kushner with Arai, by incorporating the timing circuit of Arai into the circuit of Kushner, for the purpose of allowing for the safety circuit to be used to protect from fast transient ESD fault conditions while allowing almost no leakage current to flow during normal operation.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kushner as applied to claim 1 above, and further in view of Abou-Khalil (US 2012/0080717).
With regard to claim 11, Kushner teaches the device of claim 1 and further teaches that the silicon-controlled rectifier comprises: a PNP bipolar transistor (101) and an NPN bipolar transistor (102), wherein a base (107) of the NPN bipolar transistor is connected to a collector (108) of the PNP bipolar transistor, and wherein a collector (106) of the NPN bipolar transistor is connected to a base (105) of the PNP bipolar transistor.
Kushner does not teach a resistor connected between the base of the PNP bipolar transistor and the anode.
Abou-Khalil, in Figure 1c, teaches an SCR similar to Kushner comprising an NPN and PNP transistor. It is further taught that a resistor connected between the base of the PNP bipolar transistor and the anode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kushner with Abou-Khalil, by including a resistor in the SCR, for the purpose of increasing the triggering voltage of the SCR to ensure that the device does not conduct until it is triggered.
With regard to claims 12-16, Kushner in view of Abou-Khalil discloses the device of claim 11, and further discloses that the silicon-controlled rectifier further comprises at least one diode (Abou-Khalil, DEFF1) connected between the anode and an emitter of the PNP bipolar transistor (re claim 12), wherein the silicon-controlled rectifier further comprises at least one diode (Abou-Khalil, DEFF2) connected between an emitter of the NPN bipolar transistor and the cathode (re claim 13), wherein an emitter of the PNP bipolar transistor corresponds to a p+ doping region, wherein the base of the PNP bipolar transistor corresponds to an n-well connected to the p+ doping region, wherein the collector of the PNP bipolar transistor corresponds to a p-well connected to the n-well, wherein an emitter of the NPN bipolar transistor corresponds to an n+ doping region connected to the p-well, wherein the base of the NPN bipolar transistor corresponds to the p-well, and wherein the collector of the NPN bipolar transistor corresponds to the n-well (as seen in Figs. 1 & 2 of Kushner) (re claim 14), wherein the resistor comprises a resistor corresponding to the n-well (a laterally formed SCR would necessarily comprise a resistance in the n-well) (re claim 15), further comprising a resistor connected between the gate of the silicon-controlled rectifier and the cathode (as seen in Fig. 1c of Abou-Khalil) (re claim 16).
With regard to claim 17, Kushner, in Figure 19, discloses a device comprising: a silicon controlled rectifier (100) comprising a PNP bipolar transistor (101) and a NPN bipolar transistor (102), wherein a base (107) of the NPN bipolar transistor is connected to a collector (108) of the PNP bipolar transistor, and wherein a collector (106) of the NPN bipolar transistor is connected to a base (105) of the PNP bipolar transistor; at least one first transistor (1905) connected between the base (1905) of the PNP bipolar transistor (101) and the cathode (103); and a second transistor (1903), wherein a source of the second transistor is connected to the cathode or an anode (104) of the silicon controlled rectifier, and wherein a drain of the second transistor is connected to a body of the at least one first transistor as seen in Fig. 19, both the drain of transistor 1903 and the body of transistor 1905 are coupled to node 105 of the SCR 100).
Kushner does not teach a first resistor connected between a gate of the silicon-controlled rectifier and a cathode of the silicon-controlled rectifier.
Abou-Khalil, in Figure 1C, teaches an SCR similar to Kushner wherein a first resistor is connected between a gate of the silicon-controlled rectifier and a cathode of the silicon-controlled rectifier.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kushner with Abou-Khalil, by including a resistor in the SCR, for the purpose of increasing the triggering voltage of the SCR to ensure that the device does not conduct until it is triggered.
With regard to claim 18, Kushner in view of Abou-Khalil discloses the device of claim 17, and further discloses that the at least one first transistor and the second transistor each comprise an n-channel field effect transistor (Kushner, paragraph 0079 and as seen in Fig. 19), and wherein the source of the second transistor (1903) is connected to the cathode (104).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kushner in view of Abou-Khalil as applied to claim 17 above, and further in view of Sato.
With regard to claim 21, Kushner in view of Abou-Khalil teaches the device of claim 17 and further teaches that the at least one first transistor comprises an n-channel field effect transistor (NFET).
Kushner in view of Abou-Khalil does not teach the second transistor comprises a p-channel field effect transistor (PFET), and wherein the source of the second transistor is connected to the anode.
Sato, in Figure 14, teaches an SCR protection circuit similar to Kushner wherein an SCR (21) is coupled to a first transistor (35-1 & 35-n) and a second transistor (29) coupled similarly to the transistors of Kushner. Sato further teaches that the at least one first transistor (35-1 & 35-n) comprises an n-channel field effect transistor (NFET), wherein the second transistor comprises a p-channel field effect transistor (PFET), and wherein the source of the second transistor is connected to the anode (through transistors 35-1 & 35-n).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kushner in view of Abou-Khalil with Sato, by coupling the gate of the second transistor of Kushner to a timer circuit as taught by Sato, for the purpose of allowing for the safety circuit to be used to protect from fast transient ESD fault conditions while allowing almost no leakage current to flow during normal operation.
Allowable Subject Matter
Claims 31 is allowed.
Claim 31 is allowed because the prior art does not teach or fairly suggest a first transistor connected to the base of the PNP bipolar transistor or the base of the NPN bipolar transistor; and a second transistor, wherein a drain of the second transistor is connected to a body of the first transistor, wherein the first transistor is surrounded by a first p+ region on a first p-well, and wherein the drain of the second transistor is connected to the first p+ region.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jou (US 2009/0261417) teaches an ESD protection circuit with a PMOSFET coupled to the body terminal of an NMOSFET and a timing circuit coupled to the gate of the NMOSFET in a manner similar to the trigger circuit taught by Applicant. The reference does not teach that this structure is used to trigger an SCR however.
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/Scott Bauer/Primary Examiner, Art Unit 2838