Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
The claim recites the limitation “wherein the first solder resist portion comprises a first filler of and the second solder resist portion comprises a second filler that is different from the first filler”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7-10 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 is rejected as it recites the limitation “wax-based material” in line 2. The limitation “wax-based material” renders the scope of the claim unclear because it is ambiguous what constitutes a wax-based material. Furthermore, the specification does not define the term nor provide objective criteria for determining whether a material is of wax-based. Accordingly, one of ordinary skill in the art would not be able to determine the metes and bounds of the claimed subject matter. For the same reason, claim 16 which recites the limitation “wax-based material”, and all dependent claims 8-10, respectively, thereof are rejected as well by virtue of their dependencies.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 11-15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hiroshima et al (U.S. Patent Publication 9148958 B2) hereinafter Hiroshima, and further in view of Baik et al (U.S. Patent Application Publication 20170117252 A1) hereinafter Baik.
Regarding claim 1, Hiroshima discloses (Title: Circuit Board and Electronic Device) a printed circuit board (circuit board 10, col. 3, ll. 37), divided into a printed circuit board area (printed circuit board area [PCBA] region comprising elements 14, 12b, and 13; FIG. 1A depicts PCBA) and a peripheral area surrounding the printed circuit board area (peripheral area [PA] region comprising elements 15; FIG. 1A depicts PA), the printed circuit board comprising:
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a plurality of unit printed circuit boards (elements comprising: vias 12c, col. 3, ll. 58; electro pads 13, col. 3, ll. 60; and solder storing regions 16, col. 4, ll. 66; annotated FIG. 1B depicts the unit PCB) provided in the printed circuit board area;
a base portion (wiring multilayer 12, col. 3, ll. 45) provided in the peripheral area and the printed circuit board area (as depicted in FIG. 1B), and comprising a circuit pattern portion (wiring pattern 12a, col. 3, ll. 57) and an insulating material portion (insulating layer 12b, col. 3, ll. 57-58); a
first solder resist portion (second solder resist 15, col. 4, ll. 27) provided in the peripheral area on a first surface of the base portion (a surface, col. 3, ll. 64; FIG. 1B depicts the second solder resist 15 on the top surface of the circuit board); and
a second solder resist portion (first solder resist 14, col. 4, ll. 27) provided in the printed circuit board area on the first surface of the base portion (FIG. 1B depicts the first solder resist 14 on the top surface of the circuit board),
wherein the first solder resist portion surrounds the second solder resist portion in the printed circuit board area (col. 4, ll. 59-63, “The second openings 15a surround the electrode pads 13 and the first openings 14a, respectively. The first solder resist 14 is exposed from the second openings 15a. Specifically, the first solder resist 14 extends to inner sides of the second openings 15a of the second solder resist 15”), and
wherein the first solder resist portion comprises a first filler of and the second solder resist portion comprises a second filler that is different from the first filler (col. 5, ll. 20-22, “The material of the second solder resist 15 may be different from the material of the first solder resist 14”).
However, Hiroshima fails to disclose the first solder resist portion also provided to a second surface of the base portion, the first surface being opposite to the second surface. Hiroshima also fails to disclose a second solder resist portion also provided to the second surface of the base portion.
Baik discloses (Title: Printed Circuit Boards and Semiconductor Packages Including the Same) a printed circuit board (PCB 1, ¶40) wherein a solder resist portion (solder resist layer 40, ¶58) is also provided to a second surface (bottom surface 14, ¶58) of the base portion (substrate base 10, ¶58), the first surface (top surface 12, ¶40) being opposite to the second surface (as depicted in FIG. 2A).
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Hiroshima discloses a printed circuit board shaped such that it has a peripheral area and the printed circuit board area that comprises of the plurality of unit printed circuit boards, the base, and solder resist portions arranged as directly claimed. Baik also discloses of a printed circuit board that provides a solder resist layer to a second bottom surface of the base. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the method of Baik of providing a solder resist portion to the bottom surface of Hiroshima’s printed circuit board to allow for coverage/protection of the lower surfaces, namely the bottom pad (bottom pad 24 in Baik FIG. 1A), or to allow for exposure of the bottom pad such that it may obtain a more adhesive force to a provided metal layer, hence more electrical connections (Baik ¶59).
Regarding claim 2, Hiroshima in view of Baik teaches the printed circuit board of claim 1, as detailed above, and Hiroshima further discloses wherein the printed circuit board area comprises a plurality of unit printed circuit board areas (FIG. 1A & 1B depict the PCBA comprising of two solder storing regions 16),
wherein each of the plurality of unit printed circuit boards is in at least one unit printed circuit board area of the plurality of unit printed circuit board areas (FIG. 1A & 1B depict the PCBA comprising of two solder storing regions 16), and
wherein the second solder resist portion (first solder resist 14, col. 4, ll. 27) is provided on the first surface of the base portion in each of the plurality of unit printed circuit board areas (as depicted in FIG. 1A & 1B).
Baik further teaches the application of a solder resist on a second, bottom, surface. Thus, the combination would allow for the first solder resist of Hiroshima to be applied to the bottom and top surface, in view of Baik, base portion in each of the plurality of unit printed circuit board areas to be layered with the solder resist. (Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 2 in the manner to providing a solder resist layer to both surfaces of a printed circuit board).
Regarding claim 3, Hiroshima in view of Baik teaches the printed circuit board of claim 2, as detailed above, and Baik further discloses wherein the first filler of the first solder resist portion is wrapped with hydrophobic groups (¶86, “The first binder material may be, for example, an acryl-based polymer resin. The second binder material may be, for example, an epoxy resin. The binder component of the first layer may be produced by a combination of an acryl-based polymer resin and an epoxy resin. The binder component of the second layer may be, for example, an epoxy resin”; ¶88, “Each of the first layer and the second layer may further include a filler and an additive, such as a silane coupling agent or a hardening catalyst. The hardening catalyst may be, for example, a phosphine-based, imidazole-based, or amine-based hardening catalyst. The silane coupling agent may be, for example, a mercapto silane coupling agent or an epoxy silane coupling agent. The filler may be, for example, silica”).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 3 in the manner to providing a solder resist layer to both surfaces of a printed circuit board).
Regarding claim 4, Hiroshima in view of Baik teaches the printed circuit board of claim 3, as detailed above, and Hiroshima further discloses wherein the first solder resist portion (second solder resist 15) is provided at a periphery of the second solder resist portion (first solder resist 14) on the first surface of the base portion and contacts the second solder resist portion, in each of the plurality of unit printed circuit board areas (FIG. 1B depicts the first and second solder resists 14 & 15 directly adjacent to each other such that the base directly contacts the first solder resist 14).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 4 in the manner to providing a solder resist layer to both surfaces of a printed circuit board).
Regarding claim 5, Hiroshima in view of Baik teaches the printed circuit board of claim 4, as detailed above, and Hiroshima further discloses wherein the second solder resist portion (first solder resist 14) is further provided in the peripheral area on the surface of the base portion (FIG. 1B depicts the first solder resist 14 extending in both the PCBA and PA), and
wherein the second solder resist portion in the peripheral area on the second surface is between the first solder resist portion on the surface in the peripheral area and the printed circuit board area (FIG. 1B depicts the first solder resist 14 arranged between the second solder resist 15, surface, extending in both the PCBA and PA).
However, Hiroshima fails to disclose the second solder resist portion being provided on the second surface of the base portion and arranged to be between the first solder resist portion, second surface, PCBA, and PA.
Though Hiroshima teaches such an arrangement to the top surface of the printed circuit board, it would have been obvious to a POSITA to take the method and arrangement of Hiroshima in combination with Baik which teaches the application of a solder resist on the bottom surface of a printed circuit board. Doing so would allow the second solder resist to be provided on the second surface and be located between the first solder resist portion, second surface, PCBA, and PA. (Regarding the reason to combine references, also refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 4 in the manner to providing a solder resist layer to both surfaces of a printed circuit board).
Regarding claim 6, Hiroshima in view of Baik teaches the printed circuit board of claim 3, as detailed above, and Baik further discloses wherein a weight ratio of the first filler of the first solder resist portion (second layer 34) to the first solder resist portion is greater than a weight ratio of the second filler of the second solder resist portion (first layer 32) to the second solder resist portion (¶84, “The first layer and the second layer may each include a binder component and a hardening component. A weight average molecular weight of the binder component of the first layer may be greater than that of the binder component of the second layer”; the disclosure uses “may”, being understood by a POSITA that Baik’s second layer may be equal or greater than the first layer), and
wherein a thickness of the first solder resist portion is greater than or equal to a thickness of the second solder resist portion (¶90, “The first layer may be thinner than the second layer”).
(Regarding the reason to combine references, refer to the rejection of claim 1, supra, as it is applicable to the rejection of claim 6 in the manner to providing a solder resist layer to both surfaces of a printed circuit board).
Regarding claim 11, Hiroshima discloses (Title: Circuit Board and Electronic Device) a printed circuit board (circuit board 10, col. 3, ll. 37) comprising:
a printed circuit board area (printed circuit board area [PCBA] region comprising elements 14, 12b, and 13; FIG. 1A depicts PCBA);
a peripheral area surrounding the printed circuit board area (peripheral area [PA] region comprising elements 15; FIG. 1A depicts PA);
a base portion (wiring multilayer 12, col. 3, ll. 45) provided in the peripheral area and the printed circuit board area (as depicted in FIG. 1B);
a first solder resist portion (second solder resist 15, col. 4, ll. 27) provided in the peripheral area on a first surface of the base portion (a surface, col. 3, ll. 64; FIG. 1B depicts the second solder resist 15 on the top surface of the circuit board); and
a second solder resist portion (first solder resist 14, col. 4, ll. 27) provided in the printed circuit board area on the first surface of the base portion (FIG. 1B depicts the first solder resist 14 on the top surface of the circuit board),
wherein the first solder resist portion surrounds the second solder resist portion in the printed circuit board area (col. 4, ll. 59-63, “The second openings 15a surround the electrode pads 13 and the first openings 14a, respectively. The first solder resist 14 is exposed from the second openings 15a. Specifically, the first solder resist 14 extends to inner sides of the second openings 15a of the second solder resist 15”).
However, Hiroshima fails to disclose the first solder resist portion also provided to a second surface of the base portion, the first surface being opposite to the second surface. Hiroshima also fails to disclose a second solder resist portion also provided to the second surface of the base portion.
Baik discloses (Title: Printed Circuit Boards and Semiconductor Packages Including the Same) a printed circuit board (PCB 1, ¶40) wherein a solder resist portion (solder resist layer 40, ¶58) is also provided to a second surface (bottom surface 14, ¶58) of the base portion (substrate base 10, ¶58), the first surface (top surface 12, ¶40) being opposite to the second surface (as depicted in FIG. 2A).
Hiroshima discloses a printed circuit board shaped such that it has a peripheral area and the printed circuit board area that comprises of the plurality of unit printed circuit boards, the base, and solder resist portions arranged as directly claimed. Baik also discloses of a printed circuit board that provides a solder resist layer to a second bottom surface of the base. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the method of Baik of providing a solder resist portion to the bottom surface of Hiroshima’s printed circuit board to allow for coverage/protection of the lower surfaces, namely the bottom pad (bottom pad 24 in Baik FIG. 1A), or to allow for exposure of the bottom pad such that it may obtain a more adhesive force to a provided metal layer, hence more electrical connections (Baik ¶59).
Regarding claim 12, Hiroshima in view of Baik teaches the printed circuit board of claim 12, as detailed above, and Hiroshima further discloses herein the first solder resist portion comprises a first filler and the second solder resist portion comprises a second filler that this different from the first filler (col. 5, ll. 20-22, “The material of the second solder resist 15 may be different from the material of the first solder resist 14”).
(Regarding the reason to combine references, refer to the rejection of claim 11, supra, as it is applicable to the rejection of claim 12 in the manner to providing a solder resist layer to both surfaces of a printed circuit board).
Regarding claim 13, Hiroshima in view of Baik teaches the printed circuit board of claim 12, as detailed above, and Baik further discloses wherein a weight ratio of the first filler of the first solder resist portion (second layer 34) to the first solder resist portion is greater than a weight ratio of the second filler of the second solder resist portion (first layer 32) to the second solder resist portion (¶84, “The first layer and the second layer may each include a binder component and a hardening component. A weight average molecular weight of the binder component of the first layer may be greater than that of the binder component of the second layer”; the disclosure uses “may”, being understood by a POSITA that Baik’s second layer may be equal or greater than the first layer).
(Regarding the reason to combine references, refer to the rejection of claim 11, supra, as it is applicable to the rejection of claim 13 in the manner to providing a solder resist layer to both surfaces of a printed circuit board).
Regarding claim 14, Hiroshima in view of Baik teaches the printed circuit board of claim 13, as detailed above, and Baik further discloses wherein a thickness of the first solder resist portion is greater than or equal to a thickness of the second solder resist portion (¶90, “The first layer may be thinner than the second layer”).
(Regarding the reason to combine references, refer to the rejection of claim 11, supra, as it is applicable to the rejection of claim 14 in the manner to providing a solder resist layer to both surfaces of a printed circuit board).
Regarding claim 15, Hiroshima in view of Baik teaches the printed circuit board of claim 12, as detailed above, and Baik further discloses wherein the first filler of the first solder resist portion is wrapped with hydrophobic groups (¶86, “The first binder material may be, for example, an acryl-based polymer resin. The second binder material may be, for example, an epoxy resin. The binder component of the first layer may be produced by a combination of an acryl-based polymer resin and an epoxy resin. The binder component of the second layer may be, for example, an epoxy resin”; ¶88, “Each of the first layer and the second layer may further include a filler and an additive, such as a silane coupling agent or a hardening catalyst. The hardening catalyst may be, for example, a phosphine-based, imidazole-based, or amine-based hardening catalyst. The silane coupling agent may be, for example, a mercapto silane coupling agent or an epoxy silane coupling agent. The filler may be, for example, silica”).
(Regarding the reason to combine references, refer to the rejection of claim 11, supra, as it is applicable to the rejection of claim 12 in the manner to providing a solder resist layer to both surfaces of a printed circuit board).
Regarding claim 17, Hiroshima in view of Baik teaches the printed circuit board of claim 11, as detailed above, and Hiroshima further discloses wherein the first solder resist portion (second solder resist 15) is provided at a periphery of the second solder resist portion (first solder resist 14) on the first surface of the base portion and contacts the second solder resist portion (FIG. 1B depicts the first and second solder resists 14 & 15 directly adjacent to each other such that the base directly contacts the first solder resist 14).
(Regarding the reason to combine references, refer to the rejection of claim 11, supra, as it is applicable to the rejection of claim 17 in the manner to providing a solder resist layer to both surfaces of a printed circuit board).
Regarding claim 18, Hiroshima in view of Baik teaches the printed circuit board of claim 17, as detailed above, and Hiroshima further discloses wherein the second solder resist portion (first solder resist 14) is further provided in the peripheral area on the surface of the base portion (FIG. 1B depicts the first solder resist 14 extending in both the PCBA and PA), and
wherein the second solder resist portion in the peripheral area on the surface is between the first solder resist portion on the surface in the peripheral area and the printed circuit board area (FIG. 1B depicts the first solder resist 14 arranged between the second solder resist 15, surface, extending in both the PCBA and PA).
However, Hiroshima fails to disclose the second solder resist portion being provided on the second surface of the base portion and arranged to be between the first solder resist portion, second surface, PCBA, and PA.
Though Hiroshima teaches such an arrangement to the top surface of the printed circuit board, it would have been obvious to a POSITA to take the method and arrangement of Hiroshima in combination with Baik which teaches the application of a solder resist on the bottom surface of a printed circuit board. Doing so would allow the second solder resist to be provided on the second surface and be located between the first solder resist portion, second surface, PCBA, and PA.
(Regarding the reason to combine references, refer to the rejection of claim 11, supra, as it is applicable to the rejection of claim 8 in the manner to providing a solder resist layer to both surfaces of a printed circuit board).
Regarding claim 19, Hiroshima in view of Baik teaches the printed circuit board of claim 19, as detailed above, and Hiroshima further discloses wherein the second solder resist portion is further provided in the peripheral area on the first surface of the base portion (FIG. 1B depicts the first solder resist 14 extending in both the PCBA and PA) and the second surface of the base portion (refer to the rejection of claim 18, supra, regarding the second solder resist portion being provided on the second surface), and
wherein the second solder resist portion in the peripheral area is between the first solder resist portion in the peripheral area and the printed circuit board area on each of the first surface of the base portion and the second surface of the base portion (FIG. 1B depicts the first solder resist 14 arranged between the second solder resist 15, surface, extending in both the PCBA and PA) (also refer to the rejection of claim 18, supra, regarding the second solder resist portion being provided on the second surface).
(Regarding the reason to combine references, refer to the rejection of claim 11 and 18, supra, as it is applicable to the rejection of claim 19 in the manner to providing a solder resist layer to both surfaces of a printed circuit board).
Regarding claim 20, Hiroshima discloses (Title: Circuit Board and Electronic Device) a printed circuit board (circuit board 10, col. 3, ll. 37) comprising:
a printed circuit board area (printed circuit board area [PCBA] region comprising elements 14, 12b, and 13; FIG. 1A depicts PCBA);
a peripheral area surrounding the printed circuit board area (peripheral area [PA] region comprising elements 15; FIG. 1A depicts PA);
a base portion (wiring multilayer 12, col. 3, ll. 45) provided in the peripheral area and the printed circuit board area;
a first solder resist portion (second solder resist 15, col. 4, ll. 27) comprising:
a first portion provided in the peripheral area on a first surface of the base portion (a surface, col. 3, ll. 64; FIG. 1B depicts the second solder resist 15 on the top surface of the circuit board), and
a second solder resist portion (first solder resist 14, col. 4, ll. 27) comprising:
a first portion provided in the printed circuit board area on the first surface of the base portion (FIG. 1B depicts the first solder resist 14 on the top surface of the circuit board), and
wherein the first solder resist portion surrounds the second solder resist portion in the printed circuit board area (FIG. 1B depicts second solder resist 15 directly surrounding and adjacent to the first solder resist 14).
However, Hiroshima fails to disclose the first solder resist portion provided as a second portion provided in the peripheral area on a second surface opposite to the first surface of the base portion. Hiroshima also fails to disclose the second solder resist portion provided as a second portion provided in the printed circuit board area on the second surface of the base portion.
Baik discloses (Title: Printed Circuit Boards and Semiconductor Packages Including the Same) a printed circuit board (PCB 1, ¶40) wherein a solder resist portion (solder resist layer 40, ¶58) is also provided to a second surface (bottom surface 14, ¶58) of the base portion (substrate base 10, ¶58), the first surface (top surface 12, ¶40) being opposite to the second surface (as depicted in FIG. 2A).
Hiroshima discloses a printed circuit board shaped such that it has a peripheral area and the printed circuit board area that comprises of the plurality of unit printed circuit boards, the base, and solder resist portions arranged as directly claimed. Baik also discloses of a printed circuit board that provides a solder resist layer to a second bottom surface of the base. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the method of Baik of providing a solder resist portion, comprised of the first and second solder resists as respectively claimed, to the bottom surface of Hiroshima’s printed circuit board to allow for coverage/protection of the lower surfaces, namely the bottom pad (bottom pad 24 in Baik FIG. 1A), or to allow for exposure of the bottom pad such that it may obtain a more adhesive force to a provided metal layer, hence more electrical connections (Baik ¶59).
Claims 7-10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hiroshima in view of Baik, and in further view of Jeong et al (U.S. Patent Application Publication 20090294162 A1) hereinafter Jeong.
Regarding claim 7, Hiroshima in view of Baik teaches the printed circuit board of claim 2, as detailed above.
However, both Hiroshima and Baik fail to further discloses wherein the first filler of the first solder resist portion is wrapped with wax-based material.
Jeong discloses (Title: Printed Circuit Board and Manufacturing Method Thereof) a printed circuit board wherein the first filler of the first solder resist portion is wrapped with wax-based material (¶44, “The polymer ink is injected into the inkjet head 40 and is printed on the solder resist layer 20”; ¶46, “The polymer ink used for inkjet printing in order to form the dam 30 can include an acrylate-based compound or wax”).
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Hiroshima in view of Baik teaches of a printed circuit board divided into a printed circuit board area and a peripheral area comprising a plurality of unit printed circuit boards. The combination also teaches of solder resist portions being provided in a specific arrangement on both the top and bottom surfaces of the printed circuit board to provide protection of electrical components within the unit PCBs. Jeong discloses of a printed circuit board method wherein a polymer ink, made up of acrylate-based compounds and/or wax, is provided to cover the exposed surface of the solder resist layer. Thus, it would have been obvious to one of ordinary skill in the art to take the method of Jeong, providing a polymer ink on the surface of a solder resist layer, and applying it to the solder resist layers of Hiroshima and Baik’s printed circuit board to allow formation of a dam, purposed to function as a means to prevent exposed pads from being contaminated by underfill solution during the process of injecting underfill solution (Jeong ¶41).
Regarding claim 8, Hiroshima, in view of Baik and Jeong, teaches the printed circuit board of claim 7, as detailed above, and Hiroshima further discloses wherein the second solder resist portion (first solder resist 14) is further provided in the peripheral area on the first surface of the base portion (FIG. 1B depicts the first solder resist 14 extending in both the PCBA and PA), and
wherein the second solder resist portion in the peripheral area is between the first solder resist portion in the peripheral area and the printed circuit board area on each of the first surface of the base portion of the base portion (FIG. 1B depicts the first solder resist 14 arranged between the second solder resist 15, surface, extending in both the PCBA and PA).
However, Hiroshima fails to disclose the second solder resist portion being provided on the second surface of the base portion and arranged to be between the first solder resist portion, second surface, PCBA, and PA.
Though Hiroshima teaches such an arrangement to the top surface of the printed circuit board, it would have been obvious to a POSITA to take the method and arrangement of Hiroshima in combination with Baik which teaches the application of a solder resist on the bottom surface of a printed circuit board. Doing so would allow the second solder resist to be provided on the second surface and be located between the first solder resist portion, second surface, PCBA, and PA.
(Regarding the reason to combine references, refer to the rejection of claim 1 and 7, supra, as it is applicable to the rejection of claim 8 in the manner to providing a solder resist layer to both surfaces of a printed circuit board and the method of providing polymer ink to the surface of a solder resist).
Regarding claim 9, Hiroshima, in view of Baik and Jeong, teaches the printed circuit board of claim 7, as detailed above, and Baik further discloses wherein a thickness of the first solder resist portion is greater than or equal to a thickness of the second solder resist portion (¶90, “The first layer may be thinner than the second layer”).
(Regarding the reason to combine references, refer to the rejection of claim 1 and 7, supra, as it is applicable to the rejection of claim 9 in the manner to providing a solder resist layer to both surfaces of a printed circuit board and the method of providing polymer ink to the surface of a solder resist).
Regarding claim 10, Hiroshima, in view of Baik a Jeong, teaches the printed circuit board of claim 8, as detailed above, and Hiroshima further discloses wherein a combined portion between the first solder resist portion and the second solder resist portion has a straight shape, a serrated shape, a wavy shape or a pulsed shape in the peripheral area (FIG. 1B depicts, from a side view, a serrated shape).
(Regarding the reason to combine references, refer to the rejection of claim 1 and 7, supra, as it is applicable to the rejection of claim 10 in the manner to providing a solder resist layer to both surfaces of a printed circuit board and the method of providing polymer ink to the surface of a solder resist).
Regarding claim 16, Hiroshima, in view of Baik a Jeong, teaches the printed circuit board of claim 12, as detailed above, and Jeong further discloses wherein the first filler of the first solder resist portion is wrapped with wax-based material (¶44, “The polymer ink is injected into the inkjet head 40 and is printed on the solder resist layer 20”; ¶46, “The polymer ink used for inkjet printing in order to form the dam 30 can include an acrylate-based compound or wax”).
(Regarding the reason to combine references, refer to the rejection of claim 11 and 7, supra, as it is applicable to the rejection of claim 16 in the manner to providing a solder resist layer to both surfaces of a printed circuit board and the method of providing polymer ink to the surface of a solder resist).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE REY D LEGASPI whose telephone number is (571)272-2956. The examiner can normally be reached Monday-Friday 8-5PM.
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/E.D.L./Examiner, Art Unit 3729 /THOMAS J HONG/Supervisory Patent Examiner, Art Unit 3729
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