Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 5, 6, 8, 9, 11, 15, 16, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagpal (2025/0086007) in view of Steinberger (2023/0123634).
Claim 1: Nagpal discloses: A method comprising:
building a graph of query operators for a query plan for a query, wherein: (Nagpal ¶0039 disclosing a task queue can be assigned to queue tasks represented by one or more nodes of one or more graphs; ¶0040 a thread enqueues a task, which is represented by a node in the graph; ¶0097 the framework disclosed herein is capable of querying each kernel to determine the input buffer(s) and output buffer(s) used by that kernel)
the graph represents a plurality of kernels including at least a first kernel and a second kernel, each kernel of the plurality of kernels performs a query operator of the query plan, and the second kernel performs a second operation that is dependent on a first operation performed by the first kernel; (Nagpal ¶0007 disclosing a plurality of kernels and a graph including a plurality of nodes corresponding to the plurality of kernels; ¶0034 a kernel is a specific configuration of hardware or hardware executing software that performs a designated task of the ML application; ¶0038 assignment of a task to multiple kernels, where the kernel may be of different kernel types; ¶0039 disclosing a task queue can be assigned to queue tasks represented by one or more nodes of one or more graphs and more each kernel is associated with a task queue; ¶0056 properties of each node include: a unique name, which kernel objects can process the task of the node, specifications of parameters for each associated kernel object, and a list of nodes (“child” nodes) to which the node connects defining a control flow; the child nodes of a parent node are dependent on completion of the task of the parent node)
executing the query plan on single-instruction-multiple-thread (SIMT) hardware, wherein: (Nagpal ¶0012 the graph specifies the control flow by, for each kernel, specifying a next node to be executed, a plurality of next nodes to be executed in parallel; ¶0039 a single task queue is created to queue tasks associated with multiple nodes if at least one same kernel is in the sets of kernels assigned to the multiple nodes; and threads of the kernels; ¶0046 a number of parallel threads that can execute functions of the kernel object; ¶0007 disclosing a hardware processor; see also ¶0021)
each kernel of the plurality of kernels executes on a plurality of threads of the SIMT hardware, (Nagpal ¶0046 properties of a kernel object can include…a path to a shared library that contains the functions to interface to and/or be performed by the compute circuit, a number of parallel threads that can execute functions of the kernel object)
each kernel of the plurality of kernels has an associated input buffer and output buffer, (Nagpal ¶0011 the graph specifies the data flow by defining one or more input buffers and one or more output buffers for each kernel)
each kernel has a set of counters comprising an input current index counter and input last index counter associated with the input buffer of the kernel and an output current index counter and output last index counter associated with the output buffer of the kernel, (Nagpal ¶0070 the in-action graph of a job can include a job identifier, the input data and output data of each node relevant to each node in the graph, the in-degree and out-degree of each node as the job is processed, application input parameters associated with the job)
for each iteration of the graph, each kernel processes a set of input data items from the input buffer of the kernel, writes a set of output data items to the output buffer of the kernel, and updates the set of counters of the kernel; and (Nagpal ¶0104 the data processing system implements block 508 by querying the buffer metadata specified in the kernel specification file(s); the plurality of kernels, and kernel metadata including buffer metadata, are specified in a single file or in a plurality of files; data processing system is capable of querying the file(s) to determine the buffer requirements for each of the buffers specified by the graph; the data processing system determines a set of buffers that are required or necessary to perform one job (e.g., one iteration) of the graph; the set of buffers may be the minimal set of buffers required to perform one job (e.g., iteration) of the graph; ¶0081 by specifying buffers for each kernel, in-place operations are supported; supported by the graph is where an input buffer of a selected kernel is updated directly rather than creating a new buffer to receive output from a data transformation; ¶0127 a first kernel, as executing, may write data to a device buffer as allocated)
wherein the method is performed by one or more computing devices. (Nagpal ¶0018 kernels executing in different compute circuits of the plurality of compute circuits disposed in a same device; ¶0115 the compute circuits may be homogeneous or heterogeneous compute circuits (e.g., different types of compute circuits as may be disposed in one or more different physical devices; see also Fig. 7 disclosing the data processing system)
Nagpal in view of Steinberger discloses:
the query plan is executed in a sequence of iterations of the graph on the SIMT hardware,
Nagpal discloses query plan and graph, and mentions at least one iteration, but does not explicitly disclose that the query plan is executed in a sequence of iterations of the graph on the SIMT hardware. Steinberger suggests or discloses this limitation/concept: (Steinberger ¶0004 streaming multi-processors (SMs) can execute large numbers of threads simultaneously, with each thread running the same program; hence, this arrangement is often referred to as a single instruction multiple thread (SIMT) architecture; ¶0014 processors are configured to process data samples associated with one or multiple chains or graphs of data processors, which chains or graphs describe processing steps to be executed repeatedly on data samples that are a subset of temporally ordered samples). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nagpal to include the query plan is executed in a sequence of iterations of the graph on the SIMT hardware as taught by Steinberger since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable.
responsive to determining the graph is fully processed, returning a query result set;
Nagpal discloses determining buffers required to perform one iteration of the graph, but does not explicitly disclose that responsive to determining the graph is fully processed, returning a query result set. Steinberger suggests or discloses this limitation/concept: (Steinberger ¶0004 the GPU executes assigned jobs independently of the host, either synchronously or asynchronously, and returns the results to the host). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nagpal to include responsive to determining the graph is fully processed, returning a query result set as taught by Steinberger since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Claim 11: Claim 11 is directed to one or more non-transitory storage media. Claim 11 recites limitations that are parallel in nature as those addressed above for claim 1, which is directed towards a method. Claim 11 is therefore rejected for the same reasons as set forth above for claim 1. Claim 11 also recites:
(Claim 11): One or more non-transitory storage media storing one or more sequences of instructions which, when executed by one or more computing devices, cause: (Nagpal ¶0150 “computer-readable storage medium” means a storage medium that contains or stores program instructions for use by or in connection with an instruction execution system, apparatus, or device. As defined herein, a “computer-readable storage medium” is not a transitory, propagating signal per se.)
Claim 5: The method of claim 1, wherein the input buffer and output buffer of each kernel are circular buffers. (Nagpal ¶0080 buffers X, A, B, and C are illustrated in circular form to differentiate the buffers from the kernels (e.g., nodes))
Claim 15: Claim 11 is directed to one or more non-transitory storage media. Claim 15 recites limitations that are parallel in nature as those addressed above for claim 5, which is directed towards a method. Claim 15 is therefore rejected for the same reasons as set forth above for claim 5.
Claim 6: The method of claim 1, wherein the graph is a directed acyclic graph. (Nagpal ¶0006 neural network can be defined as a directed acyclic graph in which the nodes represent the functions performed in processing an input data set; ¶0037 the work or job to be performed by an ML application can be specified as a directed acyclic graph and represented by nodes and edges in a computer system memory)
Claim 16: Claim 16 is directed to one or more non-transitory storage media. Claim 16 recites limitations that are parallel in nature as those addressed above for claim 6, which is directed towards a method. Claim 16 is therefore rejected for the same reasons as set forth above for claim 6.
Claim 8: The method of claim 1, wherein a given query operator is mapped to two or more kernels of the plurality of kernels. (Nagpal ¶0038 assignment of a task to multiple kernels, where the kernel may be of different kernel types; ¶0039 more than one kernel can be associated with one (the same) task queue)
Claim 18: Claim 18 is directed to one or more non-transitory storage media. Claim 18 recites limitations that are parallel in nature as those addressed above for claim 8, which is directed towards a method. Claim 18 is therefore rejected for the same reasons as set forth above for claim 8.
Claim 9: The method of claim 1, wherein the second operation of the second kernel depends on operations performed by two or more kernels within the plurality of kernels. (Nagpal ¶0056 properties of each node include: a unique name, which kernel objects can process the task of the node…a list of nodes (“child” nodes) to which the node connects defining a control flow; child nodes of a parent node are dependent on completion of the task of the parent node; ¶0057 dependency of a child node on a parent node can be predicated on the task of the child node requiring data provided by the parent node; ¶0040 thread enqueues a task, which is represented by a node in the graph, in a task queue in response to completion of the task(s) of the parent node(s) of that node; ¶0038 assignment of a task to multiple kernels, where the kernel may be of different kernel types)
Claim 19: Claim 19 is directed to one or more non-transitory storage media. Claim 19 recites limitations that are parallel in nature as those addressed above for claim 9, which is directed towards a method. Claim 19 is therefore rejected for the same reasons as set forth above for claim 9.
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagpal (2025/0086007) in view of Steinberger (2023/0123634) further in view of Ostrovksy (2010/0312801).
Claim 7: The method of claim 1,
wherein the query operators include a decompression operator, a join operator, or a group-by operator.
Nagpal discloses query operators, but does not explicitly disclose that the query operators include a decompression operator, a join operator, or a group-by operator. Ostrovksy suggests or discloses this limitation/concept: (Ostrovksy ¶0014 disclosing the library providing various operators (e.g., join) that the developer can combine to build data-parallel queries). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nagpal in view of Steinberger to include the query operators include a decompression operator, a join operator, or a group-by operator as taught by Ostrovksy since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Claim 17: Claim 17 is directed to one or more non-transitory storage media. Claim 17 recites limitations that are parallel in nature as those addressed above for claim 7, which is directed towards a method. Claim 17 is therefore rejected for the same reasons as set forth above for claim 7.
Claim(s) 10 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagpal (2025/0086007) in view of Steinberger (2023/0123634) further in view of Hudson (2005/0212818).
Claim 10: The method of claim 1, further comprising:
responsive to determining the graph is not fully processed, initiating a next iteration of the graph.
Nagpal discloses determining a set of buffers require to perform an iteration of the graph, but does not explicitly disclose responsive to determining the graph is not fully processed, initiating a next iteration of the graph. Hudson suggests or discloses this limitation/concept: (Hudson ¶0049 determining whether the graph requires a recursive solution to complete ordering of the graph nodes; evaluation subroutine is initiated and determines if any graph elements remain; an evaluation is made to determine if all graph elements have been ordered in the Left subset(i) and the Right subset(i); an evaluation that the graph is empty results the evaluation subroutine exiting; if the graph evaluation at step 562 results in identification of remaining graph elements, a subsequent evaluation is made to determine if more than one top-level subgraph node is included in the remaining graph elements; iteration counter variable i is incremented if only a single top-level subgraph node is identified in the remaining graph elements (step 565), and the remaining graph elements are submitted as a single graph partition to the node ordering subroutine (step 566). That is, the node ordering subroutine is called and the remaining graph elements are evaluated by returning processing to step 542 of the flowchart shown in FIG. 5B. The evaluation subroutine then exits (step 568); see also ¶0056-¶0057). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nagpal in view of Steinberger to include responsive to determining the graph is not fully processed, initiating a next iteration of the graph as taught by Hudson since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Claim 20: Claim 20 is directed to one or more non-transitory storage media. Claim 20 recites limitations that are parallel in nature as those addressed above for claim 10, which is directed towards a method. Claim 20 is therefore rejected for the same reasons as set forth above for claim 10.
Allowable Subject Matter
Claims 2-4 and 12-14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 103, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
No prior art is applied to the following claims:
Claim 2: The method of claim 1, wherein: for each given iteration of the graph, each kernel: updates the input current index counter to specify a first data item to start processing from the input buffer of the kernel in a next iteration, updates the input last index counter to specify a last data item available to be processed from the input buffer in the next iteration, updates the output current index counter to specify a first slot in the output buffer to which output has been written during the given iteration, and updates the output last index counter to specify a last slot in the output buffer to which output has been written during the given iteration.
Claim 3: The method of claim 1, wherein: the input buffer of the second kernel is the output buffer of the first kernel, and for a given iteration of the graph, the second kernel updates an output current index counter of the first kernel based on a number of data items consumed from the output buffer of the first kernel during the given iteration.
Claim 4: The method of claim 1, wherein for a given iteration of the graph, a given kernel fills the output buffer of the given kernel without consuming all data items of the input buffer of the given kernel.
Claim 12: The one or more non-transitory storage media of claim 11, wherein: for each given iteration of the graph, each kernel: updates the input current index counter to specify a first data item to start processing from the input buffer in a next iteration, updates the input last index counter to specify a last data item available to be processed from the input buffer in the next iteration, updates the output current index counter to specify a first slot in the output buffer to which output has been written during the given iteration, and updates the output last index counter to specify a last slot in the output buffer to which output has been written during the given iteration.
Claim 13: The one or more non-transitory storage media of claim 11, wherein: the input buffer of the second kernel is the output buffer of the first kernel, and for a given iteration of the graph, the second kernel updates an output current index counter of the first kernel based on a number of data items consumed from the output buffer of the first kernel during the given iteration.
Claim 14: The one or more non-transitory storage media of claim 11, wherein for a given iteration of the graph, a given kernel fills the output buffer of the given kernel without consuming all data items of the input buffer of the given kernel.
Additional Relevant Prior Art References
The following reference(s) have been identified as relevant to the applicant’s invention, but are not relied upon in the prior art rejection:
Koneru (2019/0235917)
Langhammer (2023/0333857)
Drysdale (2017/0177404)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIONE N SIMPSON whose telephone number is (571)272-5513. The examiner can normally be reached M-F; 7:30 a.m.-4:30 p.m..
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DIONE N. SIMPSON
Primary Examiner
Art Unit 3628
/DIONE N. SIMPSON/Primary Examiner, Art Unit 3628