DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 6, 9, 13 – 19, 22, 23, 28 and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2011/0240987).
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(Claim 1) Lee et al. teach a thin film transistor substrate, comprising:
a substrate (910);
a gate electrode (970) and an active layer (950) spaced apart in an up and down direction on the substrate,
wherein the active layer (950) includes a first active layer (950c) and a second active layer (950b), and the first active layer (950c) is disposed closer to the gate electrode (970) than the second active layer (950b); and
a gate insulating film (960) disposed between the first active layer (950c) and the gate electrode (970),
wherein the first active layer (950c) and the gate insulating film (960) are in contact with each other, and
wherein the first active layer (950c) includes a crystalline semiconductor material, and the second active layer (950b) includes an amorphous semiconductor material (paragraph 117).
(Claim 2) Lee et al. teach wherein the first active layer (950c) includes a crystalline oxide semiconductor material, and the second active layer (950b) includes an amorphous oxide semiconductor material paragraph 117).
(Claim 3) Lee et al. teach wherein a thickness of the first active layer (950c) is thinner than that of the second active layer (950b, paragraph 94, Table 1).
(Claim 4) Lee et al. teach wherein a carrier mobility of the first active layer is lower than that of the second active layer (paragraph 94, Table 1).
(Claim 5) Lee et al. teach wherein a bandgap energy of the first active layer is greater than a bandgap energy of the second active layer (paragraphs 61, 94 Table 2).
(Claim 6) Lee et al. teach wherein the first active layer includes at least one semiconductor material of a CuO-based oxide semiconductor material, a GaO-based oxide semiconductor material, an InO-based oxide semiconductor material, an InZnO-based oxide semiconductor material, an InGaZnO-based oxide semiconductor material, a SnO-based oxide semiconductor material, and a ZnO-based oxide semiconductor material, and
wherein the second active layer includes at least one semiconductor material of a CuO- based oxide semiconductor material, a GaO-based oxide semiconductor material, an InO-based oxide semiconductor material, an InZnO-based oxide semiconductor material, an InGaZnO-based oxide semiconductor material, a SnO-based oxide semiconductor material, and a ZnO-based oxide semiconductor material (paragraph 84).
(Claim 9) Lee et al. teach wherein the active layer (950) is disposed under the gate electrode (970).
(Claim 13) Lee et al. teach wherein the active layer (950) is disposed above the gate electrode (930).
(Claim 14) Lee et al. teach wherein the active layer further includes a third active layer (950a), the second active layer (950b) is disposed between the first active layer (950c) and the third active layer (950a), and the third active layer includes a crystalline material (paragraph 117).
(Claim 15) Lee et al. teach wherein the first active layer and the third active layer are formed of a same oxide semiconductor material (paragraph 84).
(Claim 16) Lee et al. teach wherein the gate electrode includes a first gate (970) electrode and a second gate electrode (920), the first active layer (950c) is adjacent to the first gate electrode (970), and the third active layer (950a) is adjacent to the second gate electrode (920).
(Claim 17) Lee et al. teach the thin film transistor substrate, further comprising a second gate insulating film (930) disposed between the third active layer (950a) and the second gate electrode (920), the third active layer (950a) and the second gate insulating film (930) being in contact with each other.
(Claim 18) Lee et al. teach wherein a thickness of the third active layer (950a) is thinner than that of the second active layer (950b, paragraph 94 Table 1).
(Claim 19) Lee et al. teach wherein a bandgap energy of the third active layer is greater than that of the second active layer (paragraph 62).
(Claim 22) Lee et al. teach a manufacturing method of a thin film transistor substrate comprising:
forming a second active layer (950b) including an amorphous oxide semiconductor material on a substrate (paragraph 117);
forming a first active layer (950c) including a crystalline oxide semiconductor material on the second active layer (paragraph 117);
forming a gate insulating film (960) on the first active layer; and
forming a gate electrode 970) on the gate insulating film.
(Claim 23) Lee et al. teach wherein the forming the second active layer (950b) includes forming an IZO-based amorphous oxide semiconductor (paragraph 84) by a metal organic chemical vaporized deposition MOCVD method or a sputtering method (paragraph 92).
(Claim 28) Lee et al. teach a display apparatus comprising the thin film transistor substrate (paragraphs 7, 30).
(Claim 29) Lee et al. teach the display apparatus, further comprising:
a display panel including a plurality of gate lines;
a plurality of data lines and a plurality of pixels; and
a gate driver configured to supply scan signals to the plurality of gate lines of the display panel, wherein each of the plurality of pixels comprises:
a display element, a first thin film transistor configured to supply a data voltage supplied from the data line to a second thin film transistor according to the scan signal, and the second thin film transistor configured to supply a data current to the display element according to the data voltage, and
wherein the thin film transistor substrate constitutes at least one of the first thin film transistor, the second thin film transistor and a thin film transistor of the gate driver (paragraph 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2011/0240987).
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(Claim 11) Lee et al. in the Embodiment of figure 9 lack the thin film transistor substrate, further comprising a source electrode (820a) connected to one side of the active layer and a drain electrode (820b) connected to another side of the active layer (830), wherein at least one of the source electrode (820a) and the drain electrode (820b) is in contact with the second active layer (830a).
However, Lee et al. in the Embodiment of fig. 8 teach the thin film transistor substrate, further comprising a source electrode (820a) connected to one side of the active layer and a drain electrode (820b) connected to another side of the active layer (830), wherein at least one of the source electrode (820a) and the drain electrode (820b) is in contact with the second active layer (830a) as art recognized equivalents.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references as art recognized equivalents.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2011/0240987) in view of Yano et al. (TW 1453915).
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(Claim 10) Lee et al. teach the thin film transistor substrate (910), further comprising a source electrode (940a) connected to one side of the active layer (950) and a drain electrode (940b) connected to another side of the active layer (950).
Lee et al. lack wherein at least one of the source electrode and the drain electrode is in contact with the first active layer and is not in contact with the second active layer.
However, Yano et al. teach wherein at least one of the source electrode (50) and the drain electrode (52) is in contact with the first active layer (44) and is not in contact with the second active layer (42) as an art recognized equivalent.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references as art recognized equivalents.
Claims 24 – 27 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2011/0240987) in view of Hong et al. (US 2014/0210835).
(Claim 24) Lee et al. lack wherein the forming the first active layer includes forming the first active layer by a spatiotemporally divided atomic layer deposition (STALD) method.
However, Hong et al. teach wherein the forming the first active layer includes forming the first active layer by a spatiotemporally divided atomic layer deposition (STALD) method (paragraphs 71 – 73 and 78 – 80) for the benefit of tuning the composition of the multi-component metal oxide thin film (paragraph 78).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of tuning the composition of the multi-component metal oxide thin film.
(Claim 25) Lee et al. teach wherein the forming the first active layer includes forming an IGZO-based crystalline oxide semiconductor (GaInZnO, paragraph 84).
Lee et al. lack forming an IGZO-based crystalline oxide semiconductor including supplying an In source material and an O2 reactant material, supplying a Ga source material and an O2 reactant material, and supplying a Zn source material and an O2 reactant material.
However, Hong et al. teach forming an IGZO-based crystalline oxide semiconductor including supplying an In source material and an O2 reactant material, supplying a Ga source material and an O2 reactant material, and supplying a Zn source material and an O2 reactant material (paragraphs 71 – 73 and 78 – 80) for the benefit of tuning the composition of the multi-component metal oxide thin film (paragraph 78).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of tuning the composition of the multi-component metal oxide thin film.
(Claim 26) Lee et al. teach a manufacturing method of a thin film transistor substrate comprising:
forming a first active layer (950a) including a crystalline oxide semiconductor material on a substrate (paragraph 117);
forming a second active layer (950b) including an amorphous oxide semiconductor material on the first active layer (paragraph 117);
forming a gate insulating film (960) on the second active layer; and
forming a gate electrode (970) on the gate insulating film,
wherein the forming the first active layer includes forming an IGZO-based crystalline oxide semiconductor (GaInZnO, paragraph 84), and the forming the second active layer includes forming an IZO-based amorphous oxide semiconductor (InZnO, paragraph 84).
Lee et al. lack forming an IGZO-based crystalline oxide semiconductor including supplying an In source material and an O2 reactant material, supplying a Ga source material and an O2 reactant material, and supplying a Zn source material and an O2 reactant material.
However, Hong et al. teach forming an IGZO-based crystalline oxide semiconductor including supplying an In source material and an O2 reactant material, supplying a Ga source material and an O2 reactant material, and supplying a Zn source material and an O2 reactant material (paragraphs 71 – 73 and 78 – 80) for the benefit of tuning the composition of the multi-component metal oxide thin film (paragraph 78).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of tuning the composition of the multi-component metal oxide thin film.
(Claim 27) Lee et al. lack wherein the forming the first active layer is performed at a temperature of 300 °C or more and 400 C or less.
However, Hong et al. teach wherein the forming the first active layer is performed at a temperature of 300 °C or more and 400 C or less (paragraph 80) for the benefit of tuning the composition of the multi-component metal oxide thin film (paragraph 78).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of tuning the composition of the multi-component metal oxide thin film (paragraph 78).
Allowable Subject Matter
Claims 7, 8, 12, 20 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(Claim 7) wherein a band gap energy of the first active layer is 3.0 eV or more and 3.2 eV or less, and a bandgap energy of the second active layer is 2.6 eV or more and 2.8 eV or less.
(Claim 8) wherein an electrical resistance of the first active layer is greater than that of the second active layer.
(Claim 12) wherein the at least one of the source electrode and the drain electrode is in contact with the second active layer through a contact hole provided in the first active layer.
(Claim 20) wherein an electrical resistance of the third active layer is greater than that of the second active layer.
(Claim 21) wherein a Fermi level of the active layer is closer to a conductive band of the second active layer than to the conductive band of the first active layer.
Conclusion
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IGWE U ANYA whose telephone number is (571)272-1887. The examiner can normally be reached 8:00 AM - 6:00 PM.
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
March 14, 2026