DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-11 have been considered but are moot due to the newly amended independent claims.
Response to Arguments
Applicant's arguments filed 03/13/2026 have been fully considered but they are not persuasive.
Specifically, Applicant discusses
(1) how “the function of slew rate is different from soft driving” (Remarks 03/13/2026, page 7-9; and
(2) how the claimed limitations (see Remarks 03/13/2026, page 9) are not taught by the reference because “Payne actually did not suggest three high-side PMOS power transistors which are coupled with a low-side NMOS power transistor.
In response to applicant's argument (1) that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “soft driving”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In response to applicant’s argument (2) against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Furthermore, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Here, the combined teachings of Chauhan et al. and Payne are used as a whole to teach the claimed limitations.
Regarding the claimed limitations of Claim 1 indicated by Applicant in Remarks 03/13/2026, page 9, Chauhan et al. teaches in Figure 9 an output driving circuit for power devices, comprising:
when timing signals V1, V2 and V3 respectively convert from a high level to a low level in time periods t1, t2 and t3, a first high-side PMOS power transistor, a second high-side PMOS power transistor, and a third high-side PMOS power transistor of plurality of high-side PMOS power transistors are turned on sequentially (see Figures 10 and 11), while said low-side NMOS power transistor being turned off (NMOS transistor of 902, as controlled by ND);
during said t1 to said t2 time period, said power supply starting to charge an output capacitor up to a first voltage through a first charging path having said first high-side PMOS power transistor (based on the operation of 904 to further control load components connected to PAD, including the capacitor connected to PAD in Figure 1, which is continuously charged based on the voltage at PAD);
during said t2 to said t3 time period, said power supply starting to charge said output capacitor up to a second voltage through a second charging path having said second high-side PMOS power transistor (based on the operation of 906);
during said t3 to beyond time period, said power supply starting to charge said output capacitor through a third charging path having said third high-side PMOS power transistor (based on the operation of 908 and/or 910),
wherein said first, said second and third charging paths are turned on, said output capacitor being continuously charged to a target voltage value (based in part on the control signals COMPP0-COMPP3 and control signals COMPN0-COMPN3 to further control load components connected to PAD, including the capacitor connected to PAD in Figure 1, which is continuously charged based on the voltage at PAD);
wherein said target voltage is higher than said second voltage which is higher than said first voltage (as 902 through 910 is sequentially turned on, based in part on the control signals COMPP0-COMPP3 and control signals COMPN0-COMPN3).
but does not explicitly teach each of said plurality of high-side PMOS power transistor having its source connected to a power supply through a resistor electrically connected in series between each of said plurality of PMOS power transistor and said power supply.
Payne et al. teaches in Figure 2 a high-side PMOS power transistor (50) having its source connected to a power supply (VDD) through a resistor (54) electrically connected in series between said PMOS power transistor and said power supply (wherein 54 is serially connected between 50 and VDD).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the resistor teachings of Payne et al. with the output stage module of Chauhan et al. in order to minimize the voltage drop across the high-side power transistor such that “the reference levels are largely independent of any process variation in both the sheet resistance and the transistor strength.” Payne et al. Col. 3, lines 5-9.
Thus, the claimed limitations remain taught by Chauhan et al. and Payne et al.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chauhan et al. (US 7,902,885 B2), in view of Payne et al. (US 6,624,670 B2.
Regarding Claim 1, Chauhan et al. teaches in Figure 9 an output driving circuit for power devices, comprising:
an output stage module including a plurality of high-side PMOS power transistor (each PMOS which receives PD) and a low-side NMOS power transistor (each NMOS which receives ND),
each of said plurality of high-side PMOS power transistor having its source connected to a power supply (source of each PMOS in Figure 9, which is connected to the power source),
each of said plurality of high-side PMOS power transistor having its drain electrically connected to drain of said low-side NMOS power transistor (drain of each PMOS in Figure 9 is connected to the plurality of NMOSs), and source of said NMOS power transistor connected to ground (source of each NMOS is connected to ground);
a plurality of first inverters having output terminals electrically connected to gate of said high-side PMOS power transistors to drive said high-side PMOS power transistor (using TXP; see also Figure 1: 104); and
a second inverter having output terminals electrically connected to gate of said low-side NMOS power transistor to drive said low-side NMOS power transistor (using TXN; see also Figure 1: 106);
wherein a voltage control signal is input from input terminals of said plurality of first inverters and said second inverter, used to respectively control turn-on and turn-off states of said plurality of high-side PMOS power transistors and said low-side NMOS power transistor (Col. 6, lines 45, wherein the control signals “are provided by a compensation circuit”; see also Figure 1, as both 104 and 106 are controlled by signal from node A, wherein the output of 104 controls the gate of P11 and the output of 106 controls the gate of N11);
when timing signals V1, V2 and V3 respectively convert from a high level to a low level in time periods t1, t2 and t3, a first high-side PMOS power transistor, a second high-side PMOS power transistor, and a third high-side PMOS power transistor of plurality of high-side PMOS power transistors are turned on sequentially (see Figures 10 and 11), while said low-side NMOS power transistor being turned off (NMOS transistor of 902, as controlled by ND);
during said t1 to said t2 time period, said power supply starting to charge an output capacitor up to a first voltage through a first charging path having said first high-side PMOS power transistor (based on the operation of 904 to further control load components connected to PAD, including the capacitor connected to PAD in Figure 1, which is continuously charged based on the voltage at PAD);
during said t2 to said t3 time period, said power supply starting to charge said output capacitor up to a second voltage through a second charging path having said second high-side PMOS power transistor (based on the operation of 906);
during said t3 to beyond time period, said power supply starting to charge said output capacitor through a third charging path having said third high-side PMOS power transistor (based on the operation of 908 and/or 910),
wherein said first, said second and third charging paths are turned on, said output capacitor being continuously charged to a target voltage value (based in part on the control signals COMPP0-COMPP3 and control signals COMPN0-COMPN3 to further control load components connected to PAD, including the capacitor connected to PAD in Figure 1, which is continuously charged based on the voltage at PAD);
wherein said target voltage is higher than said second voltage which is higher than said first voltage (as 902 through 910 is sequentially turned on, based in part on the control signals COMPP0-COMPP3 and control signals COMPN0-COMPN3).
but does not explicitly teach each of said plurality of high-side PMOS power transistor having its source connected to a power supply through a resistor electrically connected in series between each of said plurality of PMOS power transistor and said power supply.
Payne et al. teaches in Figure 2 a high-side PMOS power transistor (50) having its source connected to a power supply (VDD) through a resistor (54) electrically connected in series between said PMOS power transistor and said power supply (wherein 54 is serially connected between 50 and VDD).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the resistor teachings of Payne et al. with the output stage module of Chauhan et al. in order to minimize the voltage drop across the high-side power transistor such that “the reference levels are largely independent of any process variation in both the sheet resistance and the transistor strength.” Payne et al. Col. 3, lines 5-9.
Regarding Claims 2 and 7, Chauhan et al. and Payne et al., as a whole, teach all the limitations of the present invention, wherein Chauhan et al. further teaches the output driving circuit, wherein said voltage control signal is PWM signal (Col. 6, lines 45, wherein the control signals “are provided by a compensation circuit”; see also Figure 1, as both 104 and 106 are controlled by signal as inputted from node A).
Regarding Claims 3 and 10, Chauhan et al. and Payne et al., as a whole, teach all the limitations of the present invention, wherein Chauhan et al. further teaches the output driving circuit, wherein both said first inverter and said second inverter are constructed with push-pull structure (see configurations of 104 and 106).
Regarding Claim 4, Chauhan et al. and Payne et al., as a whole, teach all the limitations of the present invention, wherein Chauhan et al. further teaches the output driving circuit, wherein said first inverter includes a first PMOS transistor (P12) connected to a first NMOS transistor (N12), source of said first PMOS connected to said power supply (source of P12 connected to power supply), drain of said first PMOS transistor connected to drain of said first NMOS transistor (drain of P12 is connected to drain of N12), and source of said first NMOS transistor connected to ground (source of N12 is connected to ground).
Regarding Claim 5, Chauhan et al. and Payne et al., as a whole, teach all the limitations of the present invention, wherein Chauhan et al. further teaches the output driving circuit, wherein said second inverter includes a second PMOS transistor (P13) connected to a second NMOS transistor (N13), source of said second PMOS connected to said power supply (source of P13 connected to power supply), drain of said second PMOS transistor connected to drain of said second NMOS transistor (drain of P13 is connected to drain of N13), and source of said second NMOS transistor connected to ground (source of N13 is connected to ground).
Regarding Claim 6, Chauhan et al. teaches in Figure 9 an output driving circuit for power devices, comprising:
a plurality of high-side driving arms connected in parallel (each PMOS connected in parallel, which receives PD), each high-side driving arm having a high-side PMOS power transistor with its source connected to a power supply (source of each PMOS in Figure 9, which is connected to the power source);
a low-side driving arm (one of the NMOSs which receives ND), said low-side driving arm containing a low-side NMOS power transistor with its drain connected to common drain of said plurality of high-side driving arms (drain of each PMOS in Figure 9 is connected to the plurality of NMOSs) and its source connected to ground (source of each NMOS is connected to ground); and
an output capacitor connected between said drain of said low-side NMOS power transistor and ground (the capacitor connected to PAD in Figure 1, which is continuously charged based on the voltage at PAD) been segmentally driven through sequentially inputting timing control signals to drive each of said high-side driving arms (Col. 6, lines 45, wherein the control signals “are provided by a compensation circuit”; see also Figure 1, as both 104 and 106 are controlled by signal from node A, wherein the output of 104 controls the gate of P11 and the output of 106 controls the gate of N11);
when timing signals V1, V2 and V3 respectively convert from a high level to a low level in time periods t1, t2 and t3, a first high-side PMOS power transistor, a second high-side PMOS power transistor, and a third high-side PMOS power transistor of plurality of high-side PMOS power transistors are turned on sequentially (see Figures 10 and 11), while said low-side NMOS power transistor being turned off (NMOS transistor of 902, as controlled by ND);
during said t1 to said t2 time period, said power supply starting to charge an output capacitor up to a first voltage through a first charging path having said first high-side PMOS power transistor (based on the operation of 904 to further control load components connected to PAD, including the capacitor connected to PAD in Figure 1, which is continuously charged based on the voltage at PAD);
during said t2 to said t3 time period, said power supply starting to charge said output capacitor up to a second voltage through a second charging path having said second high-side PMOS power transistor (based on the operation of 906);
during said t3 to beyond time period, said power supply starting to charge said output capacitor through a third charging path having said third high-side PMOS power transistor (based on the operation of 908 and/or 910),
wherein said first, said second and third charging paths are turned on, said output capacitor being continuously charged to a target voltage value (based in part on the control signals COMPP0-COMPP3 and control signals COMPN0-COMPN3 to further control load components connected to PAD, including the capacitor connected to PAD in Figure 1, which is continuously charged based on the voltage at PAD);
wherein said target voltage is higher than said second voltage which is higher than said first voltage (as 902 through 910 is sequentially turned on, based in part on the control signals COMPP0-COMPP3 and control signals COMPN0-COMPN3).
but does not explicitly teach
but does not explicitly teach each high-side PMOS power transistor with its source connected to a power supply through a resistor connected in series between said high-side PMOS power transistor and said power source; and adjusting resistance value of said resistor connected between said power supply and said high-side PMOS power transistor of each of said high-side driving arms.
Payne et al. teaches in Figure 2 a high-side PMOS power transistor (50) having its source connected to a power supply (VDD) through a resistor (54) electrically connected in series between said PMOS power transistor and said power supply (wherein 54 is serially connected between 50 and VDD); and adjusting resistance value of said resistor connected between said power supply and said high-side PMOS power transistor of each of said high-side driving arms (Col. 3, lines 5-9, wherein the resistance is set so as to minimize the voltage drop across the high-side power transistor such that “the reference levels are largely independent of any process variation in both the sheet resistance and the transistor strength.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the resistor teachings of Payne et al. with the output stage module of Chauhan et al. and Graves, as a whole, in order to minimize the voltage drop across the high-side power transistor such that “the reference levels are largely independent of any process variation in both the sheet resistance and the transistor strength.” Payne et al. Col. 3, lines 5-9.
Regarding Claim 8, Chauhan et al. and Payne et al., as a whole, teach all the limitations of the present invention, wherein Chauhan et al. further teaches the output driving circuit, wherein said gate of the high-side PMOS power transistor of each of the high-side driving arms is electrically connected to an inverter for individually inputting control signal to drive said PMOS power transistor on and off (wherein each high-side PMOS gate is each connected to TXP, including an inverter 104, as further shown in Figure 1).
Regarding Claim 9, Chauhan et al. and Payne et al., as a whole, teach all the limitations of the present invention, wherein the output driving circuit, wherein said control signal is inverted with said timing control signal (see Chauhan et al.: Figure 1, as inputted at node A).
Regarding Claim 11, Chauhan et al. and Payne et al., as a whole, teach all the limitations of the present invention, wherein Chauhan et al. further teaches the output driving circuit, wherein said inverter as detailed in Figure 1 includes:
a PMOS transistor (P12) connected to an NMOS transistor (N12), source of said PMOS transistor connected to said power supply (source of P12 is connected to power supply), drain of said PMOS transistor connected to drain of said NMOS transistor (drain of P12 is connected to drain of N12), source of said NMOS transistor is grounded (source of N12 is connected to ground), and
both gate of said PMOS transistor and gate of said NMOS transistor connected together as an input terminal of said control signal (where the gates of P11 and N11 are connected together at node A through inverters 104 and 106, respectively).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
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/DIANA J. CHENG/Primary Examiner, Art Unit 2849