DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tripathi et al. (US Pub. No. 2017/0177256), hereinafter referred to as Tripathi.
Referring to claims 1 and 8, Tripathi discloses a processing system (fig. 1), comprising: a memory (fig. 1, Memory 12); a buffer configured to store sensor data (always-on component 16 may include a memory (not shown in FIG. 1) to buffer the sensor data, [0030]); at least a portion of system management circuitry (fig. 1, NOTE: the combination of PMU 156 and SOC components, e.g. PMGR 32, Always-On 16, communication fabric, etc. make up the system management circuitry; among other components, at least the PMGR 32, PMU 156, communication fabric 27,and Always-On can be considered to make up “a portion”) configured to change at least a portion of the memory from a low-power state to a regular power state (PMU 156 may generally include the circuitry to generate supply voltages and to provide those supply voltages to other components of the system such as the SOC 10, the memory 12 (V.sub.MEM in FIG. 1), [0047]) based on a usage of the buffer while at least a portion of the memory is in the low-power state (sensor capture module 44 may be programmed with a watermark or other indication of fullness in the allocation memory area (generally, e.g., a “threshold”), and the sensor capture module 44 may be configured to wake the memory controller 22 to write the captured sensor data to memory 12, [0051]), the low-power state configured to reduce power consumption by the memory (Power/energy consumption may be reduced because only the needed components are powered up, [0009]; supply various power supply voltage to the SOC, the memory 12, [0027]); and a memory controller (fig. 1, MC 22) configured to transfer the sensor data from the buffer to the at least a portion of the memory when the at least a portion of the memory is in the regular power state (the sensor capture module 44 may be configured to wake the memory controller 22 to write the captured sensor data to memory 12, [0051]), wherein the at least a portion of the system management circuity is configured to, in response to the memory controller transferring the sensor data from the buffer to the at least a portion of the memory (determine that the need to access the memory 12 has ended, [0071]): change the at least a portion of the memory from the regular power state to the low-power state (putting to sleep various components, [0060]; cause a transition back to the process state 64. The transition may include returning the memory 12 to self refresh mode, [0071]); and in response to changing the memory to the low-power state, enter a second low-power state (other components of the SOC 10 (e.g. the CPU complex 14, the peripherals 18A-18B, and the PMGR 32) are powered down, [0028]; determine that the need to access the memory 12 has ended…powering down the memory controller 22 and the communication fabric 27, [0071]; NOTE: the always-on component implements the state machine which transitions the component between various power states related to the components facilitate the transfer of the sensor data to the memory , see [0062]) configured to reduce power-consumption by the at least a portion of the system management circuitry (Power/energy consumption may be reduced because only the needed components are powered up, [0009]; processor 40 is power gated in the wait state, [0065]; the always-on component 16 may determine that memory access is completed…The state machine may transition to…wait state, [0082]).
As to claims 2 and 9, Tripathi discloses sensor data management circuitry (fig. 1-2, components of Always-On 16) configured to wake up the at least a portion of the system management circuitry based on the usage of the buffer being equal to or greater than a predetermined threshold value ([0047], [0051], [0060]).
As to claims 4 and 11, Tripathi discloses a first power rail configured to provide power to the sensor data management circuitry; and a second power rail configured to provide power to the memory, wherein the first power rail is different from the second power rail (always-on component 16 may be configured to cause a restore of the power of the components being powered up (block 90). For example, the local PMGR 48 may be configured to request that the PMU 156 restore supply voltage to one or more supply voltage rails of the SOC 10, [0089]; NOTE: Tripathi anticipates power supplied by voltage rails, and restoring power to individual components, therefore in order for component 16 to remain “always-on” the voltage supply must be separate from the power-down components, which in view of using one or more supply voltage rails indicates the rail to power 16 would be required to be different than a rail to power the memory).
As to claims 5 and 12, Tripathi discloses the at least a portion of the system management circuitry is configured to, after changing the at least a portion of the memory from the regular power state to the low-power state in response to the memory controller transferring the sensor data from the buffer to the at least a portion of the memory (sensor capture module 44 may be programmed with a watermark or other indication of fullness in the allocation memory area (generally, e.g., a “threshold”), and the sensor capture module 44 may be configured to wake the memory controller 22 to write the captured sensor data to memory 12, [0051]; determine that the need to access the memory 12 has ended…and powering down, [0071]), change the at least a portion of the memory from the low-power state to a regular power state based on the usage of the buffer being equal to or greater than a predetermined threshold value (sensor capture module 44 may be programmed with a watermark or other indication of fullness in the allocation memory area (generally, e.g., a “threshold”), and the sensor capture module 44 may be configured to wake the memory controller 22 to write the captured sensor data to memory 12, [0051]).
As to claims 6 and 13, Tripathi discloses one or more sensors (fig. 1, Sensors 20) configured to generate the sensor data, wherein the sensor data is representative of one or more user interactions ([0005-0006], [0031]).
As to claims 7 and 14, Tripathi discloses at least a portion of the memory is in the regular power state only while the memory controller transfers the sensor data from the buffer (wake the memory controller 22 to write the captured sensor data to memory 12, [0051]; determine that the need to access the memory 12 has ended…and powering down, [0071]).
As to claim 10, Tripathi discloses changing the at least a portion of the memory from the low-power state to the regular power state is in response to receiving a wake-up signal from the sensor data management circuitry ([0047], [0051], [0060]).
Referring to claim 15, Tripathi discloses a processing system (fig. 1), comprising: a memory (fig. 1, Memory 12); one or more sensors (fig. 1, Sensors 20) configured to store sensor data in a buffer (always-on component 16 may include a memory (not shown in FIG. 1) to buffer the sensor data, [0030]); and a microcontroller (fig. 1 and 12, Always-On 16) configured to: monitor a usage of the buffer by the sensor data while at least a portion of the memory is in a first power state (sensor capture module 44 may be programmed with a watermark or other indication of fullness in the allocation memory area (generally, e.g., a “threshold”), and the sensor capture module 44 may be configured to wake the memory controller 22 to write the captured sensor data to memory 12, [0051]); change at least a portion of system management circuitry (fig. 1, NOTE: the combination of PMU 156 and SOC components, e.g. PMGR 32, Always-On 16, communication fabric, etc. make up the system management circuitry; among other components, at least the PMGR 32, PMU 156, communication fabric 27,and Always-On can be considered to make up “a portion”) from a first power state to a second power state based on monitored usage of the buffer (PMU 156 may generally include the circuitry to generate supply voltages and to provide those supply voltages to other components of the system such as the SOC 10, the memory 12 (V.sub.MEM in FIG. 1), [0047]; local PMGR 48 may be configured to communicate with the PMU 156 to support state changes, as well as to manage the providing of supply voltages to various components of the SOC 10 as part of waking up or putting to sleep various components, [0060]); and, the at least a portion of system management circuitry configured to: wake the at least a portion of the memory; transfer the sensor data from the buffer to the at least a portion of the memory (the sensor capture module 44 may be configured to wake the memory controller 22 to write the captured sensor data to memory 12, [0051]); and enter the first power state in response to transferring the sensor data from the buffer to the at least a portion of the memory (may determine that the need to access the memory 12 has ended, and may cause a transition back to the process state 64. The transition may include returning the memory 12 to self refresh mode and powering down the memory controller 22 and the communication fabric 27, [0071]; NOTE: the always-on component implements the state machine which transitions the component between various power states related to the components facilitate the transfer of the sensor data to the memory , see [0062]), the first power state configured to reduce power-consumption by the at least a portion of the system management circuitry (Power/energy consumption may be reduced because only the needed components are powered up, [0009]; processor 40 is power gated in the wait state, [0065]; the always-on component 16 may determine that memory access is completed…The state machine may transition to…wait state, [0082]).
As to claim 16, Tripathi discloses the microcontroller is configured to: provide a wake-up signal to the system management circuitry (fig. 1, PMU 156) based on the monitored usage of the buffer being equal to or greater than a predetermined threshold value ([0047], [0051], [0060]).
As to claim 17, Tripathi discloses at least a portion of the system management circuitry is configured to enter the second power state in response to the system management circuitry receiving the wake-up signal ([0047], [0051], [0060]).
As to claim 18, Tripathi discloses at least portion of the system management circuitry comprises a security processor (ROM load 100 may begin at the exit of reset by the CPU processors 30 and may include reading low level boot code for the low level boot 102 from a ROM (e.g. a secure ROM), decrypting and/or authenticating the low level boot code, [0095]).
As to claim 19, Tripathi discloses a first power rail configured to provide power to the microcontroller; and a second power rail configured to provide power to the memory, wherein the first power rail is different from the second power rail (always-on component 16 may be configured to cause a restore of the power of the components being powered up (block 90). For example, the local PMGR 48 may be configured to request that the PMU 156 restore supply voltage to one or more supply voltage rails of the SOC 10, [0089]; NOTE: Tripathi anticipates power supplied by voltage rails, and restoring power to individual components, therefore in order for component 16 to remain “always-on” the voltage supply must be separate from the power-down components, which in view of using one or more supply voltage rails indicates the rail to power 16 would be required to be different than a rail to power the memory).
As to claim 20, Tripathi discloses the sensor data is representative of one or more user interactions ([0005-0006], [0031]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Tripathi in view of Ruan et al. (US Pub. No. 2024/0295972), hereinafter referred to as Ruan.
As to claim 3, Tripathi discloses the at least a portion of the system management circuitry is configured to change the at least a portion of the memory from the low-power state to the regular power state in response to receiving a wake-up signal from the sensor data management circuitry ([0047], [0051], [0060]).
While Tripathi discloses the wake-up signal correlates to a write operation in the memory at which the sensor data is to be written, Tripathi does not appear to explicitly disclose the wake-up signal indicating one or more locations in the memory to be written.
However, Ruan discloses the wake-up signal indicating one or more locations in the memory to be written (memory sub-system controller 115 can receive commands…to achieve the desired access to the memory devices…address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices, [0032]; when a wake-up event occurs, such as receiving a read or write command from the host system, [0035]).
Tripathi and Ruan are analogous art because they are from the same field of endeavor, power consumption management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Tripathi and Ruan before him or her, to modify the power management of Tripathi to include the combined write command wake-up technique of Ruan because the use of a write command to wake up the system component would reduce the required signaling, and Tripathi demonstrates that the prior art contained a “base” device (method, or product) upon which the claimed invention can be seen as an improvement, Ruan demonstrates that prior art contained a known technique (i.e., initiating a wake-up with read/write commands) that is applicable to the base device (method, or product), and one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable wake-up results and resulted in an improved system requiring less wake-up signaling.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art (MPEP 2143.I.D).
Therefore, it would have been obvious to combine Tripathi and Ruan to obtain the invention as specified in the instant claim.
Response to Arguments
Applicant's arguments filed 3/16/2026, have been fully considered but they are not persuasive.
Regarding independent claims 1, 12, and 15, rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tripathi, on pg. 7-8 of the response the Applicant asserts:
“Claim 1, as amended, recites "at least a portion of system management circuitry configured to in response to the memory controller transferring the sensor data from the buffer to the at least a portion of the memory: change the at least a portion of the memory from the regular power state to the low-power state; and enter a second low-power state of the plurality of power states configured to limit the power-consumption of the at least a portion of the system management circuitry." However, Tripathi does not disclose or suggest that, in response to data being transferred to the memory, the component that changes the memory to a low-power state also enters a second low-power state that limits the power consumption of that component…
…Once the processor has determined the need to access the system memory has ended, Tripathi discloses that the processor may return the memory to a self-refresh mode. However, Tripathi does not disclose or suggest that in response to changing the memory to the self-refresh mode, the processor then enters a low-power mode that reduces the power consumption of the processor. Instead, Tripathi discloses that, in response to determining that access to memory is no longer needed, the processor enters a process state, which is not configured to reduce the power consumption by the processor. As an example, Tripathi discloses that "[i]n the process state 64, the processor 40 may be active and executing code from the memory 42 (or out of the processor 40's cache, if any)" and is silent as to the process state being configured to reduce the power consumption of the processor. (Tripathi, [0068].) Further, Tripathi seems to suggest that the process state includes the processor functioning without restriction, noting that "the transition from the wait state 60 to the process state 64 may include powering up the processor 40, and resetting and initializing the processor 40."
The Examiner respectfully disagrees. As demonstrated in the rejections above, the limitation “at least a portion of system management circuitry” is not limited to a single component; the rejection above demonstrates how after access to the memory is completed the state machine enters “a second low-power state” wait state corresponding to components making up “at least a portion of system management circuitry” and which includes power gating such that the state “limits the power consumption”.
As to claim 3, the Applicant’s remarks on pg. 9 of the response are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC T OBERLY/ Primary Examiner, Art Unit 2184
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