Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The corrections made to the specification in the response filed on May 11, 2026 are accepted by the examiner.
Claim Objections
The objection to claim 13 is withdrawn in view of the amendments made to claim 13 in the response filed on May 11, 2026.
Claim Rejections - 35 USC § 112
The rejections of claims 14-16 under 35 U.S.C. 112(b) are withdrawn in view of the amendments made to claims 14 and 16 in the response filed on May 11, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8-10, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nongaillard et al. (FR 3078198 A1). The examiner notes that the citations to pages and lines of Nongaillard refer to pages and lines in the previously attached English language translation of Nongaillard.
Regarding Claim 1:
Nongaillard discloses a semiconductor structure, comprising:
a first semiconductor layer (channel layer, See figs. 1a-1b, 2b, ref. no. 1b and page 3 lines 1-20);
a second semiconductor layer (barrier layer, See figs. 1a-2b, ref. no. 1a and page 3 lines 1-20) disposed on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer form a heterostructure (the channel layer and the barrier layer are formed from semiconductor materials that form a heterostructure, See page 3 lines 1-20);
a gate (gate electrode, See figs. 1a-2b, ref. no. 40 and page 3 lines 10-31) disposed in a gate region (the region of the barrier layer below the gate electrode, See figs. 1a-2b, ref. nos. 1a, 40) of the second semiconductor layer; and
a plurality of spacing layers (bars made of p-type material between the barrier layer and the channel layer, See figs. 1a-2b, ref. nos. 1a, 1b, 4, and page 3 lines 22-31) arranged at intervals and between the second semiconductor layer and the first semiconductor layer along an extension direction of the gate (the plurality of bars is distributed under the gate electrode in the x-direction and each of the bars crosses the interface of the stack, See figs. 1a-2b, ref. nos. 4, 40, and page 3 lines 33-46);
wherein the plurality of spacing layers are disposed entirely between the first semiconductor layer and the second semiconductor layer (the bars made of p-type material are between the barrier layer and the channel layer with top surfaces level with the top surface of the barrier layer such that the bars made of p-type material do not extend beyond the barrier layer, See figs. 1a-2b, ref. nos. 1a, 4) such that a two-dimensional electron gas at the heterostructure is continuous along the extension direction of the gate (a two-dimensional electron gas is continuous between the bars made of p-type material in x-direction when the transistor is turned on, See fig. 1b, ref. no. 3, page 3 lines 11-20, 44-47, and page 4 lines 15-22).
Regarding Claim 2:
Nongaillard discloses wherein a length of a spacing layer of the plurality of spacing layers is greater than or equal to a length of the gate in a direction perpendicular to the extension direction of the gate (a length of one bar of the plurality of bars is greater than the length of the gate electrode in the y-direction, See figs. 2a-2b, ref. nos. 4 and 40).
Regarding Claim 3:
Nongaillard discloses wherein projection area of the plurality of spacing layers in the gate region accounts for 20% to 80% of area of the gate region (the ratio of the width of the bars to the spacing between the bars will be kept below 5/2 or even below 1, See page 4 lines 22-27. The examiner notes that for a ratio of 1 50% of the area in the gate region will be occupied by the bars and 50% of the area in the gate region will be space between the bars.).
Regarding Claim 4:
Nongaillard discloses wherein patterns of the plurality of spacing layers comprise at least one of a polygon (rectangular shape, See fig. 2a-2b, ref. no. 4 and page 4 lines 11-13), a circle (circular shape, See page 4 lines 11-13), an ellipse, or a special-shaped pattern (polygonal shape other than a rectangular shape or a square shape, See page 4 lines 11-13).
Regarding Claim 8:
Nongaillard discloses a substrate (support substrate, See page 5 lines 2-7) and a buffer layer (buffer layer, See page 5 lines 2-7), wherein the buffer layer is located between the substrate and the first semiconductor layer (the buffer layer is interposed between the support substrate and the channel layer 1b, See page 5 lines 2-7).
Regarding Claim 9:
Nongaillard discloses wherein the first semiconductor layer is a channel layer (channel layer, See figs. 1a-1b, 2b, ref. no. 1b and page 3 lines 1-20) and the second semiconductor layer is a barrier layer (barrier layer, See figs. 1a-2b, ref. no. 1a and page 3 lines 1-20); or the first semiconductor layer is a back barrier layer and the second semiconductor layer is a channel layer.
Regarding Claim 10:
Nongaillard discloses a source (source electrode, See figs. 1a, 2a-2b, ref. no. 20 and page 3 lines 11-20) and a drain (drain electrode See figs. 1a, 2a-2b, ref. no. 30 and page 3 lines 11-2), wherein the source and the drain are located on two sides of the gate in a direction parallel to the first semiconductor layer (See figs. 1a, 2a-2b, ref. nos. 20, 30, 40); and the source and the drain are located above the second semiconductor layer; or the source and the drain penetrate through the second semiconductor layer and are located on the first semiconductor layer (the source electrode and the drain electrode are located on the channel layer, See fig. 1a, ref. no. 1b, 20, 30).
Regarding Claim 12:
Nongaillard discloses a riser layer (insulating layer, See figs. 1a-2b, ref. no. 50 and page 3 lines 22-31) located between the gate and the second semiconductor layer.
Claim 14 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakagawa (US 5,726,467).
Regarding Claim 14:
Nakagawa discloses a method for preparing a semiconductor structure, comprising:
growing a first semiconductor layer (forming GaAs layer, See figs. 2(a), 3, ref. no. 3, and col. 3 lines 17-25);
growing a plurality of spacing layers (forming the insulator layers, See fig. 3, ref. no. 12 and col. 3 lines 38-54) on the first semiconductor layer;
growing a second semiconductor layer (forming n+AlGaAs layer and n+GaAs layer, See figs. 2(a), 3, ref. no. 4 and col. 3 lines 17-25) on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer form a heterostructure semiconductor materials that form a heterostructure (the examiner notes that the GaAs layer and the n+AlGaAs layer are semiconductor materials that form a heterostructure), and the plurality of spacing layers (the insulator layers cross the interface of the GaAs layer and the n+AlGaAs layer, See fig. 3, ref. no. 12) are located between the second semiconductor layer and the first semiconductor layer; and
growing a gate (forming a gate electrode, See figs. 2(d), 3, ref. no. 6 and col. 3 lines 26-33) in a gate region (the region of the n+AlGaAs layer below the gate electrode, See figs.2(d), 3, ref. no. 6) of the second semiconductor layer,
wherein the plurality of spacing layers are arranged at intervals along an extension direction of the gate (the insulator layers are located at intervals along the right to left direction of the gate electrode, See figs. 2(d), 3, ref. nos. 6, 12, and col. 3 lines 38-54), wherein the plurality of spacing layers are disposed entirely between the first semiconductor layer and the second semiconductor layer (the insulator layers are between the GaAs layer, the n+AlGaAs layer, the n+GaAs layer with top surfaces level with the top surface of the n+GaAs layer such that the insulator layers do not extend beyond the n+GaAs layer, See figs. 1a-2b, ref. nos. 1a, 4) such that a two-dimensional electron gas at the heterostructure is continuous along the extension direction of the gate (a two-dimensional electron gas is continuous between the insulator layers, See fig. 3, ref. no. 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (Work-Function Engineering in Novel High Al Composition Al0.72Ga0.28N/AlN/GaN HEMTs) in view of Morita et al. (WO 2022/230293 A1) further in view of Nakagawa (US 5,726,467). The examiner notes that the citations to paragraphs of Morita refer to paragraph of the attached English language translation.
Regarding Claim 1:
Li discloses a semiconductor structure, comprising:
a first semiconductor layer (205nm GaN layer, See figs. 2a and page 1 paragraph 2)
a second semiconductor layer (2.7nm Al0.72Ga0.28N layer, See figs. 2a and page 1 paragraph 2) disposed on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer form a heterostructure (the GaN layer and the Al0.72Ga0.28N layer form a heterostructure with an AlN spacer, See fig.2a);
a gate (gate, See fig. 2a) disposed in a gate region (the region of the 2.7nm Al0.72Ga0.28N layer below the gate, See figs. 2a) of the second semiconductor layer; and
a spacer layer (~0.6nm AlN spacer, See fig. 2a and page 1 paragraph 2),
wherein the spacer layer is disposed entirely between the first semiconductor layer and the second semiconductor layer (the AlN spacer is inserted between the GaN layer and the Al0.72Ga0.28N layer, See fig. 2a and page 1 paragraph 2) such that a two-dimensional electron gas at the heterostructure is continuous along an extension direction of the gate (two-dimensional electron gas, See fig. 2a, ref. no. 2DEG and page 1 and paragraphs 1-2. The examiner notes that the two-dimensional electron gas is continuous in the direction into the page where the Al0.72Ga0.28N layer overlays the GaN layer. The examiner also notes that forming stripes of Al0.72Ga0.28N that overlay the GaN layer will have a two-dimensional electron gas where the stripes of Al0.72Ga0.28N that overlay the GaN layer).
Li does not disclose a plurality of spacing layers arranged at intervals and between the second semiconductor layer and the first semiconductor layer along an extension direction of the gate.
Morita discloses a semiconductor device has a plurality of multiple openings arranged at intervals under a gate electrode along the extension direction of the gate electrode where the gate insulating film is in contact with the channel layer (See figs. 5-6, ref. nos. 12a, 14, 15, paragraphs 16-17 and 30-31. The examiner also notes that portions of the barrier layer 12 between the openings is also arranged at intervals under a gate electrode along the extension direction of the gate electrode.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Li to include a plurality of multiple openings arranged at intervals under a gate electrode along the extension direction of the gate electrode where the gate insulating film in in contact with a channel as taught by Morita in order to reduce heat generate by reducing current density. (See Morita paragraphs 4 and 7).
The above stated combination of Li and Morita does not disclose a plurality of spacing layers.
Nakagawa discloses narrow line channels that extend between a source and a drain (See fig. 5, ref. nos. 21, 23, 24a-24c and col. 1 lines 16-23).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Li and Morita to include extending the plurality of multiple openings arranged at intervals under a gate electrode along the extension direction of the gate electrode to extend to the source and the drain as taught by Nakagawa in order to further define separate channels. (The examiner notes that portions of the barrier layer and the AlN spacer between the openings will also extend to the source and drain.)
Regarding Claim 2:
The above stated combination of Li, Morita, and Nakagawa discloses wherein a length of a spacing layer of the plurality of spacing layers is greater than or equal to a length of the gate in a direction perpendicular to the extension direction of the gate (The examiner notes the remaining portions of the AlN spacer will extend from the source to the drain and thus have a length greater than a length of the gate in the direction perpendicular to the extension direction of the gate. See Li fig. 2a, gate and ~0.6nm AlN spacer).
Regarding Claim 5:
Li discloses wherein a range of a thickness of a spacing layer of the plurality of spacing layers is 0.1 to 2 nm (~0.6nm AlN spacer, See fig. 2a).
Regarding Claim 6:
Li discloses a range of thickness for spacing layers of approximately 0.6nm (~0.6nm AlN spacer, See fig. 2a). The range of thickness of provided by the disclosure of approximately 0.6 nm is so close to the range of the thickness of 0.1 to 0.3 nm that one skilled in the art would expect them to have the same properties. Therefore, a prima facie case of obviousness exists.
Regarding Claim 7:
Li discloses wherein a material of the plurality of spacing layers comprises AlN (~0.6nm AlN spacer, See fig. 2a).
Regarding Claim 8:
Li discloses a substrate (sapphire substrate, See fig. 2a) and a buffer layer (S.I. GaN layer, See fig. 2a), wherein the buffer layer is located between the substrate and the first semiconductor layer (the S.I. GaN layer is located between the sapphire substrate and the 205nm GaN layer, See fig. 2a).
Regarding Claim 9:
Li discloses wherein the first semiconductor layer is a channel layer (205nm GaN layer, See figs. 2a and page 1 paragraph 2. The examiner notes that the 2D electron gas is formed in the GaN layer.) and the second semiconductor layer is a barrier layer (2.7nm Al0.72Ga0.28N layer, See figs. 2a and page 1 paragraph 2); or the first semiconductor layer is a back barrier layer and the second semiconductor layer is a channel layer.
Claims 1-2 and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al. (CN 108417493 A) in view of Morita et al. (WO 2022/230293 A1) further in view of Nakagawa (US 5,726,467). The examiner notes that the citations to paragraphs of Sun refer to paragraphs of the previously attached English language translation.
Regarding Claim 1:
Sun discloses a semiconductor structure, comprising:
a first semiconductor layer (GaN layer, See figs. 2 and paragraph 104)
a second semiconductor layer (AlGaN layer, See figs. 2 and paragraph 104) disposed on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer form a heterostructure (the GaN layer and the Al0.72Ga0.28N layer form a heterostructure with an AlN spacer in a High Electron Mobility Transistor, See fig. 2 and paragraph 104);
a gate (gate, See fig. 2, ref. no. G) disposed in a gate region (the region of the AlGaN layer below the gate, See figs. 2, ref. no. G) of the second semiconductor layer; and
a spacer layer (AlN layer between the GaN layer and the AlGaN layer, See fig. 2)
wherein the spacer layer is disposed entirely between the first semiconductor layer and the second semiconductor layer (the AlN spacer is inserted between the GaN layer and the AlGaN layer, See fig. 2) such that a two-dimensional electron gas at the heterostructure is continuous along an extension direction of the gate (a two-dimensional electron gas, See fig. 2 and paragraph 17. The examiner notes that the two-dimensional electron gas is continuous in the direction into the page where the AlGaN layer overlays the GaN layer. The examiner also notes that forming stripes of AlGaN that overlay the GaN layer will have a two-dimensional electron gas where the stripes of AlGaN that overlay the GaN layer).
Sun does not disclose a plurality of spacing layers arranged at intervals and between the second semiconductor layer and the first semiconductor layer along an extension direction of the gate.
Morita discloses a semiconductor device has a plurality of multiple openings arranged at intervals under a gate electrode along the extension direction of the gate electrode where the gate insulating film is in contact with the channel layer (See figs. 5-6, ref. nos. 12a, 14, 15, paragraphs 16-17 and 30-31. The examiner also notes that portions of the barrier layer 12 between the openings is also arranged at intervals under a gate electrode along the extension direction of the gate electrode.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Sun to include a plurality of multiple openings arranged at intervals under a gate electrode along the extension direction of the gate electrode where the gate insulating film in in contact with a channel as taught by Morita in order to reduce heat generate by reducing current density. (See Morita paragraphs 4 and 7).
The above stated combination of Sun and Morita does not disclose a plurality of spacing layers.
Nakagawa discloses narrow line channels that extend between a source and a drain (See fig. 5, ref. nos. 21, 23, 24a-24c and col. 1 lines 16-23).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Sun and Morita to include extending the plurality of multiple openings arranged at intervals under a gate electrode along the extension direction of the gate electrode to extend to the source and the drain as taught by Nakagawa in order to further define separate channels. (The examiner notes that portions of the barrier layer and the AlN spacer between the openings will also extend to the source and drain, thus, there will be multiple portions of the barrier layer and the AlN spacer separated by the openings between the source and the drain.)
Regarding Claim 2:
The above stated combination of Sun, Morita, and Nakagawa discloses wherein a length of a spacing layer of the plurality of spacing layers is greater than or equal to a length of the gate in a direction perpendicular to the extension direction of the gate (The examiner notes the remaining portions of the AlN spacer will extend from the source to the drain and thus have a length greater than a length of the gate in the direction perpendicular to the extension direction of the gate. See Sun fig. 2a, gate and ~0.6nm AlN spacer).
Regarding Claim 9:
Sun discloses wherein the first semiconductor layer is a channel layer (GaN layer is a channel layer in the HEMT structure shown in figure 2, See fig. 2) and the second semiconductor layer is a barrier layer (AlGaN layer is a barrier layer in the HEMT structure shown in figure 2, See fig. 2); or the first semiconductor layer is a back barrier layer and the second semiconductor layer is a channel layer.
Regarding Claim 10:
Sun discloses a source (source, See fig. 2, ref. no. S) and a drain (drain, See fig. 2, ref. no. D), wherein the source and the drain are located on two sides of the gate in a direction parallel to the first semiconductor layer (See fig. 2, ref. nos. S, D, G); and the source and the drain are located above the second semiconductor layer (the source and the drain are located above the AlGaN layer, See fig. 2, ref. nos. S, D; or the source and the drain penetrate through the second semiconductor layer and are located on the first semiconductor layer.
Regarding Claim 11:
Sun discloses a p-GaN layer (p-GaN layer located between gate and AlGaN layer, See fig. 2) located between the gate and the second semiconductor layer.
Regarding Claim 12:
Sun discloses a riser layer (InGaN layer located between gate and AlGaN layer, See fig. 2) located between the gate and the second semiconductor layer.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Nongaillard et al. (FR 3078198 A1) in view of Saptharishi (US 2020/0411663).
Regarding Claim 13:
Nongaillard discloses the above stated semiconductor devices.
Nongaillard does not disclose wherein N first semiconductor layers and N second semiconductor layers are provided, wherein N is an integer greater than or equal to 2; in a direction perpendicular to the first semiconductor layers), the first semiconductor layers and the second semiconductor layers are arranged alternately in sequence; and the gate is disposed in a gate region of a second semiconductor layer of the second semiconductor layers (20) located in an uppermost layer; and along an extension direction of the gate, a plurality of spacing layers arranged at intervals are disposed between each of the first semiconductor layers and a respective second semiconductor layer which is disposed on each of the first semiconductor layers.
Saptharishi discloses a high electron mobility transistor the includes a plurality of channel layer and barrier layer pairs that each provide a separate 2D electron gas channel with a gate terminal form located on a gate region of the upper most barrier layer (See fig. 3, ref. nos. 36, 38, 40, 42, 44, 46, 48, and paragraph 30 and 43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Nongaillard to include repeatedly include the structure of the channel layer, the barrier layer, and the plurality of bars made of p-type material with the gate electrode located on the upper most barrier region as taught by Saptharishi in order to achieve high gain and high power at high frequencies. (See Saptharishi paragraph 58).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US 5,726,467) in view of Chen et al. (US 10,964,788) further in Chiang et al. (US 2023/0386933).
Regarding Claim 15:
Nakagawa discloses the above stated method for preparing a semiconductor structure.
Nakagawa does not disclose wherein growing the plurality of spacing layers comprises: forming the plurality of spacing layers by passing a MO source for a time ≤ 20s.
Chen discloses depositing an insulating material by metal organic chemical vapor deposition (See col. 5 lines 43-52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method for preparing a semiconductor structure of Nakagawa to include depositing an insulating material by metal organic chemical vapor deposition as taught by Chen for ease of fabrication of the semiconductor structure through the use of known fabrication techniques.
The examiner now points out that the deposition time is a result effective variable because adjusting the deposition time adjusts the thickness of the layer being deposited. The examiner next points out that deposition time is recognized by the prior art as a result-effective variable (See Chiang paragraph 56). The examiner notes that optimization of result effective variables through routine experimentation is an obviousness expedient and not a patentable distinction. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposition time of ≤ 20s to form an insulating layer of a desired thickness.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (US 5,726,467) in view of Naylor et al. (US 2023/0197836).
Regarding Claim 16:
Nakagawa discloses the above stated method for preparing a semiconductor structure. Nakagawa further discloses wherein growing the plurality of spacing layers comprises:
growing a spacing material layer on the first semiconductor layer, patterning and etching the spacing material layer to obtain the plurality of spacing layers arranged at intervals; or
making a patterned mask layer (making a pattern in the resist film, See fig. 2(b), ref. no. 9 and col. 3 lines 17-25 and 38-53) on the first semiconductor layer, selectively growing the plurality of spacing layers in a region not covered by the mask layer (depositing an insulator film into the openings in the resist film, See col. 3 lies 38-53), and removing the mask layer to obtain the plurality of spacing layers arranged at intervals (lift off of the resist film, See col. 3 lines 38-53); or
growing a spacing material layer on the first semiconductor layer, selectively passivating the spacing material layer, and converting part of the spacing material layer into a passivation layer, wherein part of the spacing material layer which is not passivated forms the plurality of spacing layers arranged at intervals.
Nakagawa is silent about etching the mask layer.
Naylor discloses a resist may be patterned by etching portions of the resist.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method for preparing a semiconductor structure of Nakagawa to include a resist may be patterned by etching portions of the resist as taught by Naylor for ease of fabrication of the semiconductor structure through the use of known lithographic techniques.
Response to Arguments
Applicant's arguments filed May 11, 2026 have been fully considered but they are not persuasive.
The applicant’s arguments regarding the shape of the two-dimensional electron gas formed in the transistor of Nongailand are not persuasive. The examiner first notes that when the transistor is in turned on a two-dimensional electron gas in the x-direction exists between the bars of p-type material. See fig. 1b, ref. nos. 3, 4, page 3 lines 11-20, 44-47, and page 4 lines 15-15. The examiner next notes that applicant’s argument regarding the shape of the two-dimensional electron gas appear to be blend together the term direction with the term distance. The examiner now notes that an extension direction is not a distance but rather is a line along which the gate lies, thus, a two-dimensional electron gas can be continuous between any two points along the line and be continuous along the extension direction. Therefore, applicant’s arguments regarding the shape of the two-dimensional electron gas formed in the transistor of Nongailand are not persuasive because Nongailand discloses when the transistor is turned on the transistor has a two-dimensional electron gas that is continuous in the x-direction between two of the bars of p-type material.
The applicant’s argument that Nakagawa is defective is not persuasive because the applicant has not presented any evidence that Nakagawa is defective. The examiner first notes that Nakagawa is presumed to be operable. See MPEP 716.07. The examiner next notes that the applicant has the burden to rebut the presumption of operability. The examiner further notes that applicant’s arguments are not evidence unless applicant’s arguments are admissions. See MPEP 2145 Section I. Thus, the applicant has not submitted any evidence that Nakagawa defective. Therefore, applicant’s argument that Nakagawa is defective is not persuasive.
The applicant’s argument that there is a lack of any reasonable motivation to combine Li, Morita, and Nakagawa because Li, Morita, and Nakagawa are nonanalgous art directed to different technical objectives is not persuasive. The examiner notes it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, Li, Morita, and Nakagawa are in the field of inventor’s endeavor because Li, Morita, and Nakagawa are all directed toward transistors form a two-dimensional electron gas. The examiner also notes that the examiner has provided rationale for combining Li, Morita, and Nakagawa in the above stated grounds of rejection. The examiner further notes that “The rationale to modify or combine the prior art does not have to be expressly stated in the prior art; the rationale may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law.” See MPEP 2144 Section I.
The applicant’s arguments regarding the shape of the two-dimensional electron gas formed in the transistor of Li, Morita, and Nakagawa are not persuasive. The examiner first notes that forming stripes of Al0.72Ga0.28N disclosed by Li that overlay the GaN layer disclosed by Li will have a two-dimensional electron gas where the stripes of Al0.72Ga0.28N that overlay the GaN layer. The examiner next notes that applicant’s argument regarding the shape of the two-dimensional electron gas appear to be blend together the term direction with the term distance. The examiner now notes that an extension direction is not a distance but rather is a line along which the gate lies, thus, a two-dimensional electron gas can be continuous between any two points along the line and be continuous along the extension direction. Therefore, applicant’s arguments regarding the shape of the two-dimensional electron gas formed in the transistor of Li, Morita, and Nakagawa are not persuasive because Li, Morita, and Nakagawa discloses because the transistor has a two-dimensional electron gas that is continuous between stripes of Al0.72Ga0.28N that overlay the GaN layer along the direction the gate electrode lies.
The applicant’s argument that there is no motivation to combine Sun, Morita, and Nakagawa because Sun, Morita, and Nakagawa are nonanalgous art directed toward different technical problems is not persuasive. The examiner notes it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, Li, Morita, and Nakagawa are in the field of inventor’s endeavor because Sun, Morita, and Nakagawa are all directed toward transistors form a two-dimensional electron gas. The examiner also notes that the examiner has provided rationale for combining Sun, Morita, and Nakagawa in the above stated grounds of rejection. The examiner further notes that “The rationale to modify or combine the prior art does not have to be expressly stated in the prior art; the rationale may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law.” See MPEP 2144 Section I.
The applicant’s arguments regarding the shape of the two-dimensional electron gas formed in the transistor of Sun, Morita, and Nakagawa are not persuasive. The examiner first notes that forming stripes of AlGaN disclosed by Sun that overlay the GaN layer disclosed by Sun will have a two-dimensional electron gas where the stripes of AlGaN that overlay the GaN layer. The examiner next notes that applicant’s argument regarding the shape of the two-dimensional electron gas appear to be blend together the term direction with the term distance. The examiner now notes that an extension direction is not a distance but rather is a line along which the gate lies, thus, a two-dimensional electron gas can be continuous between any two points along the line and be continuous along the extension direction. Therefore, applicant’s arguments regarding the shape of the two-dimensional electron gas formed in the transistor of Sun, Morita, and Nakagawa are not persuasive because Sun, Morita, and Nakagawa discloses because the transistor has a two-dimensional electron gas that is continuous between stripes of AlGaN that overlay the GaN layer along the direction the gate electrode lies.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRETT SQUIRES whose telephone number is (571)272-8214. The examiner can normally be reached Mon-Fri 8:00am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.S./Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
