DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/22/2025 has been entered.
Response to Amendment
The Applicant’s Amendment, filed 10/22/2025 has been entered. Claims 1-20 are pending in the Application.
Response to Arguments
Applicant's arguments filed 10/22/2025 with respect to the prior art rejections have been fully considered but they are not persuasive.
Regarding claim 1, the Applicant argues that the cited art Zhang (US 20130151747) fails to teach the limitation “transmit the first data to the processing element via the second interface for storing the first data in the first memory identified by the first memory address”. The Applicant submits that Zhang’s destination address is a certain address in a hard disk, not a memory address associated with the memory of the processing element. The Examiner respectfully disagrees. Contrary to the Applicant’s submission, Zhang explicitly discloses storing the data at a destination address (see para 0103, store data at a destination address designated by the co-processing request message). The Examiner further submits that any hard drive in the system and/or memory addresses in the hard drive that is allocated to store data by the processing element (e.g. the co-processor) is understood as a memory of that processing element.
Regarding claim 8, the Applicant argues that the cited art Blinzer (US 20240220115) fails to teach the limitation “retrieve data from the non-volatile storage medium based on the first request and store the data in the memory identified by the memory address”. The Applicant submits that Blinzer’s request does not “identify the address (e.g. in the cache buffer 116) where to store the data.” The Examiner respectfully disagrees. The Examiner submits that Blinzer’s request including block address (see para 0039, the preload data request 330 including block address) for storing data in the cache buffer (see para 0043, and figure 5, corresponding block address 552 in the cache buffer 116).
Based on the reasoning above, the rejections should be maintained. Please see below for the detailed rejections.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al US 20130151747, and in view of Balkan US 20180067877.
Regarding claim 1, Zhang teaches a storage device (see figure 6, parts 101, 102, 104, 107 and 103 construed the storage devices) comprising:
a non-volatile storage medium (hard disk 101);
a first interface for communicating with a computing device (interface of 102 connecting to compute node 105);
a second interface for communicating with a processing element over a data communications network (interface of 102 connecting to co-processor card 112 through 107), wherein the second interface is for accessing a network of processing elements including the processing element (network including co-processor 112, 103, see para 0077, multiple types of co-processor card, such as a floating-point operation co-processor card, a Hash operation co-processor card, a network co-processor card, and a GPU acceleration card, may be configured in a system at the same time),the processing element including a first memory (storage of co-processor card 112, see para 0083, a final storage address of data which has been completely processed by a co-processor card. In an embodiment, the destination address may be a certain address in a hard disk of a computer system); and
a processing circuit coupled to the first interface, the second interface, and the non-volatile storage medium (co-processing task management apparatus 104), the processing circuit being configured to:
receive a first request from the computing device via the first interface (see para 0070, receive at least one co-processing request message sent by a compute node in a computer system), the first request identifying a first memory address associated with the first memory (see para 0086, information such as the request compute node identifier, the request type, the source address, the length of the to-be-processed data, the destination address and the request priority may be added into a co-processing request message);
retrieve first data from the non-volatile storage medium based on the first request (see para 0089, according to the address information which is of the to-be-processed data and carried in the co-processing request message, obtain the to-be-processed data); and
transmit the first data to the processing element via the second interface for storing the first data in the first memory identified by the first memory address (see para 0103, store data at a destination address designated by the co-processing request message, where the data has been completely processed by the idle co-processor card).
But Zhang fails to teach the first interface is based on a first interface protocol and the second interface is based on a second interface protocol different from the first interface protocol.
However, Balkan discloses a storage device including a bridge having a first interface based on a first interface protocol and a second interface based on a second interface protocol different from the first interface protocol (see figure 2 bridge 46 and claim 8, the first interface is configured to communicate using a first protocol, and the second interface is configured to communicate using a second protocol that is different than the first protocol).
Therefore, it would have been obvious to modify the device of Zhang and incorporate interfaces having different protocols.
The motivation for doing so is to allow devices with different protocols working together, thus improving the versatility of the system.
Regarding claim 2, Zhang further teaches the first interface is configured for communication with the computing device over a data communication bus (see para 0031, PCIe bus exchange).
Regarding claim 3, Zhang further teaches the second interface is configured for point-to-point communication with the processing element over the data communications network (see para 0141, the co-processor card 112 and the public buffer card 103 are inserted into PCIE slots of an input/output box 107, and the input/output box 107 is connected to the bus exchanger 102 through the PCIE bus e.g. PCIe is a point-to-point network).
Regarding claim 4, Zhang further teaches the data communications network includes a switch for transmitting the first data to the processing element based on the first memory address (see figure 6, 102 and/or 107 as the switch for transmitting data).
Regarding claim 5, Zhang further teaches the processing element includes a graphics processing unit (GPU) (see para 0040, co-processor card such as a GPU acceleration card).
Regarding claim 6, Zhang further teaches the processing circuit is further configured to transmit the first data to the processing element based on identifying a condition associated with the first memory address (see para 0103, store data at a destination address designated by the co-processing request message e.g. condition based on the destination address).
Regarding claims 16-19, please refer to the rejection of claims 1-3 and 6 since the claimed subject matter is substantially similar. The claims drawn to the method performed by the storage device addressed above.
Claims 8-15 are rejected under 35 U.S.C. 103 as being unpatentable over the Zhang et al US 20130151747, in view of Blinzer et al US 20240220115 and in view of Balkan US 20180067877.
Regarding claim 8, Zhang teaches a storage device (see figure 6, parts 101, 102, 104, 107 and 103 construed the storage devices) comprising:
a non-volatile storage medium (hard disk 101);
a memory (buffer 103);
a first interface for communicating with a computing device (interface of 102 connecting to compute node 105);
a second interface for communicating with a processing element over a data communications network (interface of 102 connecting to co-processor card 112 through 107); and
a processing circuit coupled to the first interface, the second interface, the non-volatile storage medium, and the memory (co-processing task management apparatus 104), the processing circuit being configured to:
receive a first request from the computing device via the first interface (see para 0070, receive at least one co-processing request message sent by a compute node in a computer system);
retrieve data from the non-volatile storage medium based on the first request (see para 0089, according to the address information which is of the to-be-processed data and carried in the co-processing request message, obtain the to-be-processed data), and store the data in the memory (see para 0134, obtain the to-be-processed data, and store the to-be-processed data in the public buffer card 103).
But Zhang fails to teach the first request identifying a memory address associated with the memory, and the data is stored in the in the memory identified by the memory address; receive a second request from the processing element over the second interface, the second request identifying the memory address storing the data; and based on the second request, retrieve the data from the memory and transmit the data to the processing element over the data communications network.
However, Blinzer teaches a request identifying a memory address associated with the memory, and the data is stored in the in the memory identified by the memory address (see figure 3 and para 0039, the preload data request 330 includes a block address and corresponding data offset in the file system 332 that contains the mipmap range… The NVMe driver 306 preloads the indicated mipmap range as a set of data from the file system 332 into addresses in the cache buffer 116); receive a second request from a processing element over a second interface, the second request identifying the memory address storing the data; and based on the second request (see para 0040, the data load request 120 includes the translated subset address block 350 information corresponding to the subset of prestored data 124 in the subset of prestored data 118 that corresponds to the determined LOD. For example, the shader 310 issues the data load request 120 for the cache buffer 116), retrieve the data from the memory and transmit the data to the processing element over the data communications network (see para 0040, The DMA load operation stores the subset of prestored data 124 from the cache buffer 116 into local memory 110 of the GPU).
Therefore, it would have been obvious to modify the invention of Zhang and further incorporate an address for storing the data in the buffer memory so that the co-processor can request the data from the same address.
The motivation for doing so is to reduce overhead and latency for the co-processor by reducing CPU involvement in obtaining data for the co-processor as taught by Blinzer (see para 0012).
The combination of Zhang and Blinzer fails to teach the first interface is based on a first interface protocol and the second interface is based on a second interface protocol different from the first interface protocol.
However, Balkan discloses a storage device including a bridge having a first interface based on a first interface protocol and a second interface based on a second interface protocol different from the first interface protocol (see figure 2 bridge 46 and claim 8, the first interface is configured to communicate using a first protocol, and the second interface is configured to communicate using a second protocol that is different than the first protocol).
Therefore, it would have been obvious to modify the device of Zhang and incorporate interfaces having different protocols.
The motivation for doing so is to allow devices with different protocols working together, thus improving the versatility of the system.
Regarding claim 9, Zhang further teaches the memory is exposed to the data communications network via the second interface (see para 0140, the co-processor card 112, the hard disk 101, and the public buffer card 103 may all be directly connected to the bus exchanger 102 through a PCIE bus).
Regarding claim 10, Blinzer further teaches the first request is a first read request (see para 0011, a system file I/O read) and the second request is a second read request (see para 0040, the data load request 120 for the cache buffer 116 as a direct memory access (DMA) load (read)).
Regarding claim 11, Zhang further teaches the first interface is configured for communication with the computing device over a data communication bus (see para 0031, PCIe bus exchange).
Regarding claim 12, Zhang further teaches the second interface is configured for point-to-point communication with the processing element over the data communications network (see para 0141, the co-processor card 112 and the public buffer card 103 are inserted into PCIE slots of an input/output box 107, and the input/output box 107 is connected to the bus exchanger 102 through the PCIE bus e.g. PCIe is a point-to-point network).
Regarding claim 13, Zhang further teaches the data communications network includes a switch for transmitting the first data to the processing element based on the first memory address (see figure 6, 102 and/or 107 as the switch for transmitting data).
Regarding claim 14, Zhang further teaches the processing element includes a graphics processing unit (GPU) (see para 0040, co-processor card such as a GPU acceleration card).
Regarding claim 15, Blinzer further teaches the processing element is configured to transmit the second request in response to a third request received by the processing element from the computing device, wherein the third request is for performing a computation using the data (see para 0039, The application 302 also provides the mipmap range 338 in the form of LOD to the address block translator 336. The file content may be distributed across several blocks/sectors of the storage device. The address block translator 336 is a table that allows identifying what block contains the data to be read and is precomputed for the GPU so that the GPU simply request the appropriate address in the cache buffer).
Allowable Subject Matter
Claims 7 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The known prior arts fail to explicitly disclose “The storage device further comprising a second memory, wherein the processing circuit is further configured to: receive a second request from the computing device via the first interface; process second data based on the second request for generating processed second data; store the processed second data in the second memory; receive a third request from the computing device via the first interface, the third request identifying a second memory address associated with the second memory; and transmit the processed second data to the processing element via the second interface for storing the second data in the first memory based on the second memory address” in combination with other limitation found in the independent claims 7 and 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ellis et al US 20160306553 discloses a storage device having a processing element for processing memory operation command and storing data in a non-volatile medium
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/PHONG H DANG/Primary Examiner, Art Unit 2184