DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 10/31/2023, 03/25/2025 and 01/13/2026 has been considered and placed in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 15 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by HUANG et al. (U.S. 2012/0229207).
Regarding claim 15, Huang et al. (hereinafter, Ref~207) discloses (please see fig. 2 and related text for details) an apparatus comprising:
first amplifier circuitry (top channel of Fig. 2) having a first input (Vin-), a second input (Vin+), and an output (Vout1 of Fig. 2); and
second amplifier circuitry (bottom channel of Fig. 2) including:
third amplifier circuitry (e.g. 244/264 of Fig. 2) having a first input (Vin-), a second input (Vin+), and an output (SDri2 of Fig. 2), the first input of the third amplifier circuitry coupled (via C1 of Fig. 2) to the first input (Vin-) of the first amplifier circuitry and the output of the first amplifier circuitry (please note that Vin- is coupled to Vout1 via feedback resistor as shown in Fig. 2), the second input (Vin+) of the third amplifier circuitry coupled to the second input (Vin-) of the first amplifier circuitry as seen;
and output stage circuitry (284 of Fig. 2) having an input (SDri2 of Fig. 2) and an output (Vout2), the input of the output stage circuitry coupled to the output of the third amplifier circuitry, the output of the output stage circuitry coupled (via feedback resistor) to the second input of the first amplifier circuitry as seen, meeting claim 15.
Allowable Subject Matter
Claims 16-20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Allowable Subject Matter
Claims 1-14 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claims 1-7 are allowed over the prior art of record. The prior art of record, considered individually or in combination, fails to fairly teach or suggest the claimed circuit comprising, among other limitations and unobvious limitations of “class AB amplifier circuitry having a first input, a second input, a third input, and an output, the first input of the class AB amplifier circuitry coupled to the first input of the class D amplifier circuitry and the output of the class D amplifier circuitry, the second and third inputs of the class AB amplifier circuitry coupled to the second and third inputs of the class D amplifier circuitry, and the output of the class AB amplifier circuitry.” structurally and functionally interconnected with other limitations in the manner as cited in the claims.
Claims 8-14 are allowed over the prior art of record. The prior art of record, considered individually or in combination, fails to fairly teach or suggest the claimed circuit comprising, among other limitations and unobvious limitations of “second amplifier circuitry including: modulator circuitry having a first input, a second input, a first output, and a second output, the first input of the modulator circuitry coupled to the first input of the first amplifier circuitry and the output of the first amplifier circuitry, the second input of the modulator circuitry coupled to the second input of the first amplifier circuitry; combination circuitry having a first input, a second input, and an output, the first input of the combination circuitry coupled to the first output of the modulator circuitry, the second input of the combination circuitry coupled to the second output of the modulator circuitry; feedforward circuitry having a first input, a second input, and an output, the first input of the feedforward circuitry coupled to the output of the combination circuitry, the second input of the feedforward circuitry coupled to the output of the first amplifier circuitry; comparison circuitry having an input and an output, the input of the comparison circuitry coupled to the output of the feedforward circuitry; and output stage circuitry having an input and an output, the input of the output stage circuitry coupled to the output of the comparison circuitry, the output of the output stage circuitry coupled to the first input of first amplifier and the first input of the modulator circuitry.” structurally and functionally interconnected with other limitations in the manner as cited in the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843