DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/11/26 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4, 6-14, 16-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8, 9, 11-16, 18, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al., US 20220397591 in view of Homma et al., US 20110267038 in view of Kong et al., US 20220045640.
Regarding claim 1, Zhao discloses a hybrid current sense system comprising:
a switch coupled to a phase output and coupled to a voltage rail (Fig. 1; Phases U, V, W with low and high side switches LS_U, HS_U);
an amplifier coupled to the switch and the amplifier configured to detect a current information of the switch (Fig. 1; 110 coupled to LS_U);
an analog-to-digital converter coupled to the amplifier and a current calibrator, the analog to digital converter configured to supply a digital output representative of the current information to the current calibrator (Fig. 1; ADC 118; controller 106;);
a current detector coupled between the switch and the voltage rail, the current detector configured to determine a measured current for the switch (Fig. 1; shunt resistor 114 and amp 116 to ground);
the current calibrator configured to receive the digital output and further configured to calibrate the current information of the switch based on the measured current (fig. 1; controller 106; current information used to compensate the RDSon current sensing).
Zhao further teaches a simultaneous sampling ADC which comprises first and second analog converter inputs (Fig. 1; multiple inputs to ADC 118) and wherein the ADC is configured to provide multiple digital outputs (¶[0045]; simultaneous sampling of phase currents). Zhao does not explicitly disclose that the ADC comprises a first and second ADC configured to supply a digital output and a second digital output representative of the current information to the current calibrator; the second analog to digital converter coupled between the current detector and the current calibrator; wherein the current calibrator is configured to receive the digital output and the second digital output.
Homma teaches an ADC comprising a first and second ADC circuit configured to supply a first and second digital signal output representative of an electrical measurement and a circuit which is coupled to the first and second ADC (Fig. 2; ADC 211-213); the second analog to digital converter coupled between a current detector and a current calibrator (Fig. 2; ADC 211-215 between sensor 201-205 and processing circuit 231); wherein the current calibrator is and configured to receive the digital output and a second digital output (Fig. 2; ADC 211-215 to processing device 231). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Hommainto Zhao for the benefit of providing a simultaneous processing.
Zhao as modified is silent in the analog-to-digital converter being placed in a phase detection layer and the second analog-to-digital converter being separate from the phase detection layer. Kong teaches an analog-to-digital converter being placed in a first layer and a second analog-to-digital converter being separate from the first layer (Fig. 6; ADC 14 located on a first layer, ADC 16 located on a different layer ). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Kong into Zhao as modified for the benefit of hierarchically designing a control system.
Regarding claim 2, Zhao discloses wherein: the current detector is a current-sense amplifier coupled to a shunt resistor (Fig. 1; 114, 116).
Regarding claim 3, Zhao discloses wherein: the current calibrator is configured to calibrate the current information for an on-state resistance of the switch (¶[0046]).
Regarding claim 4, Zhao discloses wherein: the current calibrator is configured to calibrate the current information for a temperature of the switch (¶[0046]).
Regarding claim 6, Zhao discloses a hybrid current sense system comprising: a high-side switch coupled to a phase output and coupled to a high voltage rail (Fig. 1; Phases U, V, W with low and high side switches LS_U, HS_U); a low-side switch coupled to the phase output and coupled to a low voltage rail (Fig. 1; Phases U, V, W with low and high side switches LS_U, HS_U); an amplifier coupled to the low-side switch and the amplifier configured to detect a first current information of the low-side switch (Fig. 1; 110 coupled to LS_U); an analog-to-digital converter coupled to the amplifier and configured to supply a digital output representative of the current information (Fig. 1; ADC 118); a current detector configured to determine a measured current for the low-side switch (Fig. 1; shunt resistor 114 and amp 116 to ground); and a current calibrator coupled to the analog-to-digital converter, with the current calibrator configured to receive the digital output and further configured to calibrate the first current information for the low-side switch based on the measured current (fig. 1; controller 106; current information used to compensate the RDSon current sensing).
Zhao further teaches a simultaneous sampling ADC which comprises first and second analog converter inputs (Fig. 1; multiple inputs to ADC 118) and wherein the ADC is configured to provide multiple digital outputs (¶[0045]; simultaneous sampling of phase currents). Zhao does not explicitly disclose that the ADC comprises a first and second ADC configured to supply a digital output and a second digital output representative of the current information; wherein the current calibrator is coupled to the first and second ADC and configured to receive the digital output and the second digital output.
Homma teaches an ADC comprising a first and second ADC circuit configured to supply a first and second digital signal output representative of an electrical measurement and a circuit which is coupled to the first and second ADC (Fig. 2; ADC 211-213); the second analog to digital converter coupled between a current detector and a current calibrator (Fig. 2; ADC 211-215 between sensor 201-205 and processing circuit 231); wherein the current calibrator is and configured to receive the digital output and a second digital output (Fig. 2; ADC 211-215 to processing device 231). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Hommainto Zhao for the benefit of providing a simultaneous processing.
Zhao as modified is silent in the analog-to-digital converter being placed in a phase detection layer and the second analog-to-digital converter being separate from the phase detection layer. Kong teaches an analog-to-digital converter being placed in a first layer and a second analog-to-digital converter being separate from the first layer (Fig. 6; ADC 14 located on a first layer, ADC 16 located on a different layer ). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Kong into Zhao as modified for the benefit of hierarchically designing a control system.
Regarding claim 8, Zhao discloses wherein: the current detector is configured to detect the measured current during a T1 state of a pulse-width modulated signal cycle, wherein the T1 state corresponding to an active state of the low side switch (¶[0045]).
Regarding claim 9, Zhao discloses further comprising: a controller configured to determine a temperature of the low-side switch based on the first current information of the low-side switch and the measured current (¶[0046]).
Regarding claim 11, Zhao discloses method of manufacturing a hybrid current sense system comprising: coupling a switch to a phase output and to a voltage rail(Fig. 1; Phases U, V, W with low and high side switches LS_U, HS_U); coupling an amplifier to the switch, the amplifier configured to detect a first current information of the switch (Fig. 1; 110 coupled to LS_U); coupling an analog-to-digital converter to the amplifier, the analog to digital converter configured to supply a digital output representative of the first current information (Fig. 1; ADC 118); configuring a current detector to determine a measured current for the switch(Fig. 1; shunt resistor 114 and amp 116 to ground);
configuring a current calibrator to calibrate the first current information for the switch based on the measured current (fig. 1; controller 106; current information used to compensate the RDSon current sensing and/or to implement diagnostic monitoring of RDSon and/or transistor junction temperature).
Zhao further teaches a simultaneous sampling ADC which comprises first and second analog converter inputs (Fig. 1; multiple inputs to ADC 118) and wherein the ADC is configured to provide multiple digital outputs (¶[0045]; simultaneous sampling of phase currents). Zhao does not explicitly disclose coupling a second analog to digital converter to the current detector, the second analog to digital converter configured to supply a second digital output representative of the measured current.
Homma teaches an ADC comprising a first and second ADC circuit configured to supply a first and second digital signal output representative of an electrical measurement and a circuit which is coupled to the first and second ADC (Fig. 2; ADC 211-213); the second analog to digital converter coupled between a current detector and a current calibrator (Fig. 2; ADC 211-215 between sensor 201-205 and processing circuit 231); wherein the current calibrator is and configured to receive the digital output and a second digital output (Fig. 2; ADC 211-215 to processing device 231). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Hommainto Zhao for the benefit of providing a simultaneous processing.
Zhao as modified is silent in the analog-to-digital converter being placed in a phase detection layer and the second analog-to-digital converter being separate from the phase detection layer. Kong teaches an analog-to-digital converter being placed in a first layer and a second analog-to-digital converter being separate from the first layer (Fig. 6; ADC 14 located on a first layer, ADC 16 located on a different layer ). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Kong into Zhao as modified for the benefit of hierarchically designing a control system.
Regarding claim 12, Zhao discloses wherein: coupling the current detector includes coupling a current-sense amplifier and a shunt resistor between the switch and the voltage rail (Fig. 1; 114, 116).
Regarding claim 13, Zhao discloses wherein: configuring the current calibrator includes configuring the current calibrator to calibrate the first current information for an on-state resistance of the switch (¶[0046]).
Regarding claim 14, Zhao discloses wherein: configuring the current calibrator includes configuring the current calibrator to calibrate the first current information for a temperature of the switch (¶[0046]).
Regarding claim 16, Zhao discloses wherein: coupling the switch to the voltage rail includes coupling a low-side switch to a low voltage rail; and further comprising: coupling a high-side switch to the phase output and to a high voltage rail (Fig. 1; low and high side switches LS_U, HS_U)).
Regarding claim 18, Zhao discloses wherein: coupling the current detector includes coupling the current detector configured to detect the measured current during a T1 state of a pulse-width modulated signal cycle (¶[0046]).
Regarding claim 19, Zhao discloses further comprising: configuring a controller to determine a temperature of the low-side switch based on the first current information of the low-side switch and the measured current (¶[0046]).
Claim 7, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al., US 20220397591 in view of Homma et al., US 20110267038 in view of Kong et al., US 20220045640 in view of Nakatake, US 20120126791
Regarding claim 7, Zhao is silent in a second amplifier coupled to the high-side switch, the second amplifier configured to detect a second current information of the high-side switch; and wherein: the current calibrator is configured to calibrate the second current information for the high-side switch based on the measured current. Nakatake teaches second amplifier coupled to the high-side switch, the second amplifier configured to detect a second current information of the high-side switch; and wherein: the current calibrator is configured to calibrate the second current information for the high-side switch based on the measured current (Fig. 2; high side and low side switches both have current measurement devices 30 which includes an amplifier). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Nakatake into Zhao for the benefit of detecting a current in the high side components as well as the low side components with greater accuracy.
Regarding claim 17, Zhao is silent in coupling a second amplifier to the high-side switch, the second amplifier configured to detect a second current information of the high-side switch; and wherein: configuring the current calibrator includes configuring the current calibrator to calibrate the second current information of the high-side switch based on the measured current. Nakatake teaches coupling a second amplifier to the high-side switch, the second amplifier configured to detect a second current information of the high-side switch; and wherein: configuring the current calibrator includes configuring the current calibrator to calibrate the second current information of the high-side switch based on the measured current (Fig. 2; high side and low side switches both have current measurement devices 30 which includes an amplifier). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Nakatake into Zhao for the benefit of detecting a current in the high side components as well as the low side components with greater accuracy.
Claim(s) 10, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al., US 20220397591 in view of Homma et al., US 20110267038 in view of Kong et al., US 20220045640 in view of Schweitzer, III et al., US 20210111586
Regarding claim 10, Zhao is silent in wherein: the current calibrator is configured to determine a Kirchhoff derived current for the high-side switch based on the measured current. Schweitzer teaches a calibrator configured to determine a Kirchhoff derived current based on the measured current (¶[0065]). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schweitzer into Zhao for the benefit of determining a current reading in case of defective reading in an auxiliary device.
Regarding claim 20, Zhao is silent in wherein configuring the current calibrator includes configuring the current calibrator to determine a Kirchhoff derived current for the high-side switch based on a measured current. Schweitzer teaches configuring a calibrator configured to determine a Kirchhoff derived current based on a measured current (¶[0065]). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schweitzer into Zhao for the benefit of determining a current reading in case of defective reading in an auxiliary device.
8. Claim(s) 21, 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al., US 20220397591 in view of Homma et al., US 20110267038 in view of Kong et al., US 20220045640 in view of Li et al., US 20200319248
Regarding claim 21, Zhao is silent in wherein the analog-to-digital converter includes a calibration voltage trigger to read the amplifier. Li teaches an analog-to-digital converter includes a calibration voltage trigger to read a circuit (Fig. 2; ADC trigger signal 238). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Li into Zhao as modified so that an improper voltage can be detected.
Regarding claim 22, Zhao is silent in wherein the second analog-to-digital converter includes a second calibration voltage trigger to read the current detector. Li teaches an analog-to-digital converter includes a calibration voltage trigger to read a circuit (Fig. 2; ADC trigger signal 238). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Li into Zhao as modified so that an improper voltage can be detected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/FEBA POTHEN/ Examiner, Art Unit 2858
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