DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
1. Claims 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/22/26.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent No. 11,521,937 Verhaverbeke et al.
2. Referring to claim 1, Verhaverbeke et al. teaches an integrated circuit comprising a plurality of blocks, (Figures 4A-C & 13E #305 & 626 & Col. 13 Lines 20-22), wherein each of the plurality of blocks comprises: devices formed in a device layer, (Figures 4A-C & 13E #302), between a front-side wiring layer, (Figures 4A-C & 13E #1370a), and a backside wiring layer, (Figures 4A-C & 13E #1370b); and a block guard-ring, (Figures 4A-C & 13E #403), surrounding the devices, wherein the block guard-ring comprises a first through silicon via, (Figures 4A-C & 13E #303 & 844), extending from a first backside pattern of the backside wiring layer, (Figures 4A-C & 13E #1370b), toward the front-side wiring layer, (Figures 4A-C & 13E #1370a), and wherein the first backside pattern is configured to apply a first supply voltage, (Figures 4A-C & 13E #1370a & Col. 28 Lines 35-36 “common ground”), or a second supply voltage provided to at least one of the devices.
3. Referring to claim 13, Verhaverbeke et al. teaches an integrated circuit comprising a plurality of blocks, (Figures 4A-C & 13E #305 & 626 & Col. 13 Lines 20-22), wherein each of the plurality of blocks comprises: devices formed in a device layer, (Figures 4A-C & 13E #302), between a front-side wiring layer, (Figures 4A-C & 13E #1370a), and a backside wiring layer, (Figures 4A-C & 13E #1370b); and a block guard-ring, (Figures 4A-C & 13E #403), surrounding the devices, and wherein the block guard-ring, (Figures 4A-C & 13E #403), comprises: a plurality of first through silicon vias, (Figures 4A-C & 13E #303 & 844), arranged in a first horizontal direction in a first portion of the block guard-ring, (Figures 4A-C & 13E #403), and passing through the device layer, the first portion extending in the first horizontal direction; and a plurality of second through silicon vias, (Figures 4A-C & 13E #303 & 844), arranged in a second horizontal direction in a second portion of the block guard-ring, (Figures 4A-C & 13E #403), and passing through the device layer, (Figures 4A-C & 13E #302), the second portion extending in the second horizontal direction intersecting with the first horizontal direction.
4. Referring to claim 14, Verhaverbeke et al. teaches an integrated circuit of claim 13, wherein each of the plurality of first through silicon vias, (Figures 4A-C & 13E #303 & 844), and the plurality of second through silicon vias, (Figures 4A-C & 13E #303 & 844), is connected to a backside pattern of the backside wiring layer, (Figures 4A-C & 13E #1370b).
5. Referring to claim 15, Verhaverbeke et al. teaches an integrated circuit of claim 14, wherein each of the plurality of first through silicon vias, (Figures 4A-C & 13E #303 & 844), and the plurality of second through silicon vias, (Figures 4A-C & 13E #303 & 844), is electrically connected to at least one of the devices via a front-side pattern, (Figures 4A-C & 13E #1370a), of the front-side wiring layer.
6. Referring to claim 16, Verhaverbeke et al. teaches an integrated circuit of claim 13, wherein each of the plurality of first through silicon vias, (Figures 4A-C & 13E #303 & 844), and the plurality of second through silicon vias, (Figures 4A-C & 13E #303 & 844), is configured to receive a first supply voltage or a second supply voltage provided to at least one of the devices, (Figures 4A-C & 13E #1370a & Col. 28 Lines 35-36 “common ground”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 11,521,937 Verhaverbeke et al.
7. Referring to claim 17, Verhaverbeke et al. teaches an integrated circuit of claim 13, wherein the plurality of blocks comprise semiconductor dies, but is silent to wherein the plurality of blocks comprise at least one of: a block including active devices configured to process analog signals; a block including at least one capacitor; a block including at least one diode; and a block including at least one resistor.
The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to know that a semiconductor die would comprises of multiple electrical devices that would include resistive and capacitive components and/or parasitic resistive and capacitive elements, and also since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
8. Claims 2-12 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
9. The prior art teaches the claimed matter in the rejections above, but is silent with respect to the above teachings in combination with the integrated circuit of claim 1, wherein the block guard-ring further comprises a plurality of gate electrodes extending parallel to each other in a first horizontal direction and arranged in a second horizontal direction crossing the first horizontal direction, and wherein the first through silicon via is disposed under a region between a first gate electrode and a second gate electrode among the plurality of gate electrodes; the integrated circuit of claim 1, wherein the block guard-ring further comprises a second through silicon via extending from a second backside pattern of the backside wiring layer toward the front-side wiring layer, wherein the first backside pattern is configured to receive the first supply voltage, and wherein the second backside pattern is configured to receive the second supply voltage; the integrated circuit of claim 1, further comprising: a chip guard-ring surrounding the plurality of blocks, wherein the chip guard-ring comprises a through silicon via extending from a backside pattern of the backside wiring layer toward the front-side wiring layer; and/or the integrated circuit of claim 13, further comprising: a chip guard-ring surrounding the plurality of blocks, wherein the chip guard-ring comprises a through silicon via extending from a backside pattern of the backside wiring layer toward a-the front-side wiring layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR A MANDALA whose telephone number is (571)272-1918. The examiner can normally be reached on M-Th 8-6:30 EST.
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/VICTOR A MANDALA/Primary Examiner, Art Unit 2899 4/29/26
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