DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections – 35 USC§ 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9, 13-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over St. Germain (US 2017/0201467 A1) hereinafter Germain ‘167 in view of Metzgen (US 2023/0023021 A1).
Regarding claims 1 and 13, Germain ‘467 teaches, a circuit comprising ([0020] and Fig. 1, a crosspoint switch matrix 100 that routes data between input and outputs):
a first switch matrix configured to receive a first plurality of input signals, and output a first intermediate signal([0020], [0031], [0032] and Figs. 1, 3, group of pint cells(e.g. group 314.2) the receives input signals via input pathways and outputs a selected signal to an “output main path” 334.2. The group of point cells reads on the first switch matrix, while the signal on the output main path reads on the firs intermediate signal);
a second switch matrix configured to receive a second plurality of input signals, and output a second intermediate signal([0031], [0032] and Fig. 3, an upstream group of point cells(e.g. group 314.1) that receives input signals and outputs a selected signal to its respective output main path 334.1. the precoding group reads on second switch matrix and its output main path carries the second intermediate signal) ;
a first switch configured to receive (i) the second intermediate signal from the second switch matrix and (ii) a first auxiliary signal, and output, a single signal output of the first switch, a second auxiliary signal([0031], [0032] and Fig. 3, a multiplexer (e.g. 332.1) receives the signal from the output main path 334.1 alongside a potential upstream bypass path signal, and selects one to outputs as a single discrete signal. The selected single signal is driven onto the output bypass path 336.2 to the next group, acting as the second auxiliary signal);
and a second switch configured to receive (i) the first intermediate signal from the first switch matrix and (ii) the second auxiliary signal from the first switch, and output, a single signal output of the first switch, an output signal([0031], [0032], [0036] and Fig. 3, a downstream multiplexer (e.g. 332.2) receives the signal from its local output main path 334.2 and the signal from the upstream output bypass path 336.2. selects between these two path and outputs a single signal to a downstream multiplexer or a final output).
Germain ‘467 does not explicitly teach that its tiles as distinct switch matrices(first and second switch matrix) rather describes its tiles as components used to form a larger switch matrix.
Metzgen ‘021 teaches, partitioning an interconnect into first and second switch matrices connected through intermediate ports and redirection circuit([0075]-[0078] and Figs. 6-8).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to implement respective point-cell tiles or groups of Germain ‘467 as distinct first and second switch matrices, as taught by Metzgen ‘021. The modification would have predictably provided a modular and scalable switching architecture with improved routing capability while retaining Germain ‘467 cascaded multiplexers, each of which selects and outputs a single signal from a local matrix path or an upstream auxiliary/bypass path.
Regarding claim 2 the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations, Metzgen ‘021 further teaches, a third switch matrix configured to receive a third plurality of input signals and output a third intermediate signal( [0027], [0106], [0107] , a third switch matrix capable of directing signals received at the second intermediate ports to multiple fourth intermediate ports); and a third switch configured to receive (i) the third intermediate signal from the third switch matrix and (ii) a third auxiliary signal, and output the first auxiliary signal that is received by the second switch( [0026], [0106], [0107] and Figs. 6-8, the matrix 622 can recursively comprise the same circuit architecture, including a third and four switch matrix and secondary bypass links (which functions as auxiliary signals)).
Regarding claim 3 the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations, Metzgen ‘021 further teaches, wherein the first switch matrix is further configured to output a third intermediate signal([0077] and Figs. 6-8, switch matrix 622 outputting multiple intermediate signals via port 634), wherein the second switch matrix is further configured to output a fourth intermediate signal( [0075], [0082] and Figs. 6-8, the switch matrix 620 outputting plurality of intermediate signals 630), wherein the output signal is a first output signal([0074], and Figs. 7-8, corresponds to the output B0), and wherein the circuit further comprises:
a third switch configured to receive (i) the fourth intermediate signal from the second switch matrix and (ii) a third auxiliary signal, and output a fourth auxiliary signal([0082] and Fig. 7, the second switch within the redirecting layer 624(e.g. switch 200-14) which receives signal from a first intermediate port 630(forth intermediate signal) and auxiliary input then output to a primary bypass link 626 (fourth auxiliary signal)); and a fourth switch configured to receive (i) the third intermediate signal from the first switch matrix and (ii) the fourth auxiliary signal from the third switch, and output a second output signal([0097] and Fig. 7, switch 200-22 which receives the signal from a third intermediate port 634 and the signal from primary bypass link 626 to output signal B1).
Regarding claim 4, the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations, Metzgen ‘021 further teaches, wherein the first switch matrix is further configured to output a fifth intermediate signal([0077] and Figs. 6-8, switch matrix 622 outputting multiple intermediate signals via port 634), wherein the second switch matrix is further configured to output a sixth intermediate signal( [0075], [0082] and Figs. 6-8, the switch matrix 620 outputting plurality of intermediate signals 630), and wherein the circuit further comprises: a fifth switch configured to receive (i) the sixth intermediate signal from the second switch matrix and (ii) a fifth auxiliary signal, and output a sixth auxiliary signal([0082] and Fig. 7, the second switch within the redirecting layer 624(e.g. switch 200-15) which receives signal from a first intermediate port 630(forth intermediate signal) and auxiliary input then output to a primary bypass link 626 (fourth auxiliary signal)); and a sixth switch configured to receive (i) the fifth intermediate signal from the first switch matrix and (ii) the sixth auxiliary signal from the fifth switch, and output a third output signal([0097] and Fig. 7, switch 200-23 which receives the signal from a third intermediate port 634 and the signal from primary bypass link 626 to output signal B2).
Regarding claim 5, the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations, Metzgen ‘021 further teaches, wherein the first switch matrix and the second and fourth switches provide a first switch matrix module ([0082]- [0083] and Figs. 6-8, the switch matrix 622 and the plurality of switches in the redirection layer 628), and
the second switch matrix and the first and third switches provide a second switch matrix module ([0081]- [0083] and Figs. 6-8, switch matrix 620 and the plurality of switches within the redirection layer 624), wherein the first and second switch matrix modules have the same design ([0108] an Figs. 6-8, the matrices 620 and 622 and the redirection layers 624 and 628 can be instances of the same circuit with equivalent properties).
Regarding claim 6, the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations, Metzgen ‘021 further teaches, wherein the output signal is a first output signal received by an output module( [0074] an Figs. 6-7, mapping to circuit output B0) , and wherein the circuit further comprises: a third switch matrix configured to receive a third plurality of input signals, and output a third intermediate signal([0079], [0106] and Figs. 6-8, a scalable system 600 which includes matrices 600 and 622, these recursive instances provide additional matrices required to handle large input signals); a fourth switch matrix configured to receive a fourth plurality of input signals, and output a fourth intermediate signal([0079], [0106] and Figs. 6-8, a scalable system 600 which includes matrices 600 and 622, these recursive instances provide additional matrices required to handle large input signals);
a third switch configured to receive (i) the fourth intermediate signal from the fourth switch matrix and (ii) a third auxiliary signal, and output a fourth auxiliary signal ([0066] and Fig. 7, switch 200-14 receiving matrix signal and auxiliary pass signal to output a primary by pass link 626(fourth auxiliary signal)); and a fourth switch configured to receive (i) the third intermediate signal from the third switch matrix and (ii) the fourth auxiliary signal from the third switch([0096] and Fig. 7, switch 200-22 it combines the matrix signal with bypass signal to output second output signal B1)., and output a second output signal to the output module( [0096] and Fig. 7, switch 200-22 it combines the matrix signal with bypass signal to output second output signal B1, both B0 and B1 can b routed to the same destination module).
Regarding claim 7, the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations Germain ‘467 further teaches, wherein the first switch matrix is configured to output a selected one of the first plurality of input signals as the first intermediate signal, or to allow the first intermediate signal to be electrically floating, or to output a ground signal as the first intermediate signal( [0022], [0033], [0045] and Figs. 1, 3, 8, an enabled point cell passes the signal present at its input toward the corresponding output multiplexer, and only one point cell may be enabled at a time in an output pathway. Thus, the mapped matrix outputs a selected one of its plurality of input signals as the local intermediate signal, notice the claim limitation is written in alternative form thus examiner is required to show only one of the alternative claim limitations).
Regarding claim 8, the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations Germain ‘467 further teaches, wherein the second switch matrix is configured to output a selected one of the second plurality of input signals as the second intermediate signal, or to allow the second intermediate signal to be electrically floating, or to output a ground signal as the second intermediate signal([0002], [0033], [0045] and Figs. 1, 3, 8, an activated point cell passes the signal present at its input to the corresponding output path, and Germain ‘467 permits only one point cell to be enabled at a time in an output pathway. The mapped second matrix therefore outputs a selected one of its input signals as the second intermediate signal, notice the claim limitation is written in alternative form thus examiner is required to show only one of the alternative claim limitations).
Regarding claim 9, the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations, Metzgen ‘021 further teaches, wherein: the first switch is configured to output a selected one of the second intermediate signal or the first auxiliary signal as the second auxiliary signal([0082], [0093]-[0095] and Figs. 6-8, the redirection layer 624 comprising switches configured to direct a signal from the matrix(intermediate signal) to either a bypass link or a next stage); and the second switch is configured to output a selected one of the first intermediate signal or the second auxiliary signal as the output signal( [0096]-[0098] and Figs. 6-8, the redirection layer 628 which comprises switches selects between signals from the bypass link(auxiliary signal) and the matrix outputs(intermediate signals)).
Regarding claim 14 the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations, Metzgen ‘021 further teaches, receiving, by a third switch matrix, a third plurality of input signals; outputting, by the third switch matrix, a third intermediate signal ( [0027], [0106], [0107] , a third switch matrix capable of directing signals received at the second intermediate ports to multiple fourth intermediate ports); receiving, by a third switch, the third intermediate signal from the third switch matrix and a third auxiliary signal; and outputting, by the third switch, the first auxiliary signal that is received by the first switch ( [0026], [0106], [0107] and Figs. 6-8, the matrix 622 can recursively comprise the same circuit architecture, including a third and four switch matrix and secondary bypass links (which functions as auxiliary signals)).
Regarding claim 15, the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations, Metzgen ‘021 further teaches, wherein: outputting, by the first switch matrix, the first intermediate signal comprises outputting a selected one of the first plurality of input signals as the first intermediate signal ([0077] and Fig. 7, matrix switch 622 outputting one of the selected input signals received via port 632); and outputting, by the second switch matrix, the second intermediate signal comprises outputting a selected one of the second plurality of input signals as the second intermediate signal([0076] and fig. 7, switch matrix 620 outputting one of the inputs 102 into intermediate port 624 ).
Regarding claim 16, the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations, Metzgen ‘021 further teaches, outputting, by the first switch, the second auxiliary signal comprises outputting a selected one of the second intermediate signal or the first auxiliary signal as the second auxiliary signa ([0082], [0093]-[0095] and Figs. 6-8, the redirection layer 624 comprising switches configured to direct a signal from the matrix(intermediate signal) to either a bypass link or a next stage and outputting, by the second switch, the output signal comprises outputting a selected one of the first intermediate signal or the second auxiliary signal as the output signal ( [0096]-[0098] and Figs. 6-8, the redirection layer 628 which comprises switches selects between signals from the bypass link(auxiliary signal) and the matrix outputs(intermediate signals)).
Regarding claim 17, Germain ‘467 teaches, a circuit ([0020] and Fig. 1, a crosspoint switch matrix 100 that routes data between input and outputs): comprising: a switch matrix configured to receive a plurality of input signals, and output (i) a selected one of the plurality of input signals as a first intermediate signal and (ii) another selected one of the plurality of input signals as a second intermediate signal(); [0020], [0021] and Fig. 1, the switch matrix includes M input pathways (120.1-120.M) that receive multiple input signals and route them to point cells(e.g. 110_1,1). When activated, these point cells output selected input signals to distinct, separate output pathways (e.g. 130.1 and 130.2), which act as the first and second intermediate signals),
a first switch to receive the first intermediate signal and a first auxiliary signal, and output, a single signal output of the first switch, a first output signal([0022], [0031] and Figs. 1, 3, a multiplexer (e.g. 132.j or 332.2) on the firs output pathway receives a signal from an output main path(the firs intermediate signal) and an output bypass path(the firs auxiliary signal). The multiplexer is configured to select between these paths to output exactly one discrete signal to its terminus, reading on the single signal output requirement); and
a second switch to receive the second intermediate signal and a second auxiliary signal, and output, a single signal output of the second switch, a second output signal([0022], [0031] and Figs. 1, 3, a corresponding multiplexer on a second output pathway(e.g. a multiple on pathway 130.2)( receives its local output main path signal (the second intermediate signal) and an upstream bypass path signal (the second auxiliary signal).The second multiplexer similarly selects between its two input paths to obtain one discrete signal as a second output signal).
Germain ‘467 does not explicitly teach that its tiles as distinct switch matrices(first and second switch matrix) rather describes its tiles as components used to form a larger switch matrix.
Metzgen ‘021 teaches, partitioning an interconnect into first and second switch matrices connected through intermediate ports and redirection circuit([0075]-[0078] and Figs. 6-8).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to implement respective point-cell tiles or groups of Germain ‘467 as distinct first and second switch matrices, as taught by Metzgen ‘021. The modification would have predictably provided a modular and scalable switching architecture with improved routing capability while retaining Germain ‘467 cascaded multiplexers, each of which selects and outputs a single signal from a local matrix path or an upstream auxiliary/bypass path.
Regarding claim 18, the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations, Germain ‘467 further teaches wherein the switch matrix is a first switch matrix, the plurality of input signals is a first plurality of input signals([0043]-[0046] and Figs. 8-9, a first modular PxQ), and wherein the circuit further comprises: a second switch matrix configured to receive a second plurality of input signals[0043]-[0046] and Figs. 8-9, multiple connected modular PxQ matrix tile),, and output a selected one of the second plurality of input signals as a third intermediate signal([0002], [0033], [0045] and Figs. 8, 9, multiple modular PxQ matrix tiles , each having multiple input pathways. An upstream tile is mapped as the second switch matrix receiving the second plurality of signals); and a third switch to receive the third intermediate signal and a third auxiliary signal, and output the first auxiliary signal that is received by the first switch([0002], [0033], [0045] and Figs. 2, 8, multiplexers are connected in cascade so that the selected output of an upstream multiplexer is carried on the bypass path to the next downstream multiplexer).
Regarding claim 20, the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations, Metzgen ‘021 further teaches, a third switch matrix and a fifth switch configured to generate the third auxiliary signal ([0026], [0106], [0107] and Figs. 6-8, the matrix 622 can recursively comprise the same circuit architecture, including a third switch matrix and fifth switch to generate third bypass links (which functions as auxiliary signals)).
Claims 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Germain ‘467 and Metzgen ‘021 as applied to claims above, and further in view of Tillman et al(US 2010/0203860 A1).
Regarding claim 10, the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations except, wherein the first auxiliary signal is an electrically floating signal or an electrically grounded signal.
Tillman ‘860 teaches, wherein the first auxiliary signal is an electrically floating signal or an electrically grounded signal ([0033] and Fig. 5, electrically grounded signal being used as an input to a switch, notice the claim limitation is written in alternative form thus examiner is required to show only one of the alternative claim limitations).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined communication system of Germain ‘467 and Metzgen ‘021, by incorporating the teaching of Tillman ‘860, since such modification would provide a calibration circuit for reducing second-order inter-modulation distortion, originating from imbalance between devices, in a differential passive mixer, as suggested by Tilman 860([0001]).
Regarding claim 19, the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations except, wherein the third auxiliary signal is an electrically floating signal, is a ground signal, or is a radio frequency (RF) input signal.
Tillman ‘860 teaches, wherein the third auxiliary signal is an electrically floating signal, is a ground signal, or is a radio frequency (RF) input signal ([0033] and Fig. 5, electrically grounded signal being used as an input to a switch, notice the claim limitation is written in alternative form thus examiner is required to show only one of the alternative claim limitations).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined communication system of Germain ‘467 and Metzgen ‘021, by incorporating the teaching of Tillman ‘860, since such modification would provide a calibration circuit for reducing second-order inter-modulation distortion, originating from imbalance between devices, in a differential passive mixer, as suggested by Tilman 860([0001]).
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable Germain ‘467 and Metzgen ‘021as applied to claims above, and further in view of Becker et al(US 2012/0262007 A1).
Regarding claim 11, the combination of Germain ‘467 and Metzgen ‘021teaches all of the claim limitations except, wherein the first and second plurality of input signals are radio frequency (RF) signals.
Becker ‘007 teaches, wherein the first and second plurality of input signals are radio frequency (RF) signals ([0042], [0051], switch matrix configured for switching RF signals).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined communication system of Germain ‘467 and Metzgen ‘021, by incorporating the teaching of Becker ‘007, since such modification would provide a simple and effective systems and method for designing and implementing topologies for switching, as suggested by Becker ‘007([0006]).
Regarding claim 12, the combination of Germain ‘467 and Metzgen ‘021 teaches all of the claim limitations except, a printed circuit board (PCB) or printed wiring board (PWB) comprising the circuit of claim 1.
Becker ‘007 teaches, a printed circuit board (PCB) or printed wiring board (PWB) comprising the circuit of claim 1([0047], [0049]-[0050], switching matrix maybe implemented on PCB or PWB).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined communication system of Germain ‘467 and Metzgen ‘021, by incorporating the teaching of Becker ‘007, since such modification would provide a simple and effective systems and method for designing and implementing topologies for switching, as suggested by Becker ‘007([0006]).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AWET A HAILE whose telephone number is (571)270-3114. The examiner can normally be reached Monday through Friday 8:30 AM - 4:30 PM EST.
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/AWET HAILE/Primary Examiner, Art Unit 2474
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