DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/11/26 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2006/0267672) in view of Lo (US 2023/0316975).
Regarding claim 1, Huang discloses a gamma line interconnect circuit comprising: a resistor string comprising a first resistor connected between a first node and a second node and a second resistor connected between the second node and a third node (abstract, ¶ 5, fig. 6, ¶ 27, resistor circuit 410);
a first switch connected between a first gamma line and the first node, and configured to operate based on an interconnect signal (fig. 6, ¶ 27, e.g., first charge-sharing switch 616 controlled by signal S1);
a second switch connected between a second gamma line and the second node, and configured to operate based on the interconnect signal (fig. 6, ¶ 27, e.g., second charge-sharing switch 616 controlled by signal S1);
and a third switch connected between a third gamma line and the third node, and configured to operate based on the interconnect signal (fig. 6, ¶ 27, e.g., third charge-sharing switch 616 controlled by signal S1),
wherein the first to third switches are turned on based on the interconnect signal, at a first time period to operate the gamma line interconnect circuit in a coarse restore mode to reduce a voltage level swing of a victim gamma line (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, frame, line, and dot-inversion disclosed, charge sharing performed for a predetermined period before polarity switch),
and wherein the first to third switches are turned off at a second time period after the first time period to operate in a fine restore mode to restore a voltage level of the victim gamma line (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, frame, line, and dot-inversion disclosed, charge sharing performed for a predetermined period before polarity switch).
Huang fails to disclose the switches are turned on in response to a change in a gray level value provided to a first source drive circuit connected with the first to third gamma lines to operate the gamma line interconnect circuit in a coarse restore mode to reduce a voltage level swing of a victim gamma line caused by the change in the gray level value.
Lo teaches the switches are turned on in response to a change in a gray level value provided to a first source drive circuit connected with the first to third gamma lines to operate the gamma line interconnect circuit in a coarse restore mode to reduce a voltage level swing of a victim gamma line caused by the change in the gray level value (fig. 12, ¶ 90-100, when display data changes, switches are operated to boost mode to rapidly settle and stabilize the gamma voltages).
Huang and Lo are both directed to gamma voltage generating circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Huang with the device of Lo since such a modification rapidly settles and stabilizes the gamma voltages (Lo, ¶ 93) and reduces power consumption (Lo, ¶ 99).
Regarding claim 2, Huang discloses wherein: each of the first switch, the second switch, and the third switch is turned on when the interconnect signal is at a logic high state, and each of the first switch, the second switch, and the third switch is turned off when the interconnect signal is at a logic low state (fig. 6, ¶ 27, charge-sharing switches 616 controlled by signal S1; see also ¶ 24).
Regarding claim 3, Lo further teaches wherein: the interconnect signal transitions from the logic low state to the logic high state at a first time point in response to the change in the gray level value to initiate the coarse restore mode, and the first time point is a start time of the first time period (fig. 12, ¶ 90-100, when display data changes, switches are operated to boost mode to rapidly settle and stabilize the gamma voltages).
Regarding claim 4, Huang discloses wherein: the interconnect signal transitions to the logic low state at a second time point after a first time length elapses from the first time point, and the second time point is an end time point of the first time period (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, frame-inversion disclosed, charge sharing performed for a predetermined period before polarity switch).
Regarding claim 5, Huang discloses wherein: after the first time point, the first source drive circuit operates based on a voltage level of the first gamma line (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, gamma voltages outputted to source driver for pixel driving).
Regarding claim 6, Huang discloses wherein: at a third time point after a second time length elapses from the second time point, the voltage level of the first gamma line reaches a voltage level that is equal to the voltage level of the first gamma line before the first time point (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 24-30, frame-inversion disclosed, charge sharing performed for a predetermined period before polarity switch in subsequent frames; e.g., switches 412 turned on to provide gamma voltages).
Regarding claim 7, Huang discloses wherein: the first time length is greater than the second time length (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 24-30, line-inversion or frame-inversion disclosed, time periods may encompass plural line or frame inversion periods).
Regarding claim 8, Huang discloses a first current provide circuit connected to the first node and configured to operate between the first time point and the second time point (figs. 6-7, ¶ 27-30, e.g., first charge-sharing switch 616 controlled by signal S1);
a second current provide circuit that is connected to the second node and configured to operate between the first time point and the second time point (figs. 6-7, ¶ 27-30, e.g., second charge-sharing switch 616 controlled by signal S1);
and a third current provide circuit that is connected to the third node and configured to operate between the first time point and the second time point (figs. 6-7, ¶ 27-30, e.g., third charge-sharing switch 616 controlled by signal S1).
Regarding claim 9, Huang discloses wherein: the first node is configured to receive a first hold voltage through a first hold line (figs. 6-7, ¶ 27-30, e.g., node at V0),
and the third node is configured to receive a second hold voltage through a second hold line (figs. 6-7, ¶ 27-30, e.g., node at V2).
Regarding claim 10, Huang discloses wherein: a voltage level of the first hold voltage corresponds to a voltage level of the first gamma line (figs. 6-7, ¶ 27-30, e.g., node at V0),
and a voltage level of the second hold voltage corresponds to a voltage level of the third gamma line (figs. 6-7, ¶ 27-30, e.g., node at V2).
Regarding claim 11, Huang discloses wherein: the first gamma line, the second gamma line, and the third gamma line are connected to an output node of different gamma amplifiers (fig. 7, ¶ 30, buffers 718).
Regarding claim 12, Huang discloses a display drive circuit comprising: a source drive circuit configured to control a display panel (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, source driver 13);
a gamma voltage generator respectively providing a first to N-th gamma voltages to a first to N-th gamma lines connected to the source drive circuit, wherein N is an integer greater than 2 (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, reference voltage generation circuit 600);
and a gamma line interconnect circuit configured to interconnect the first to N-th gamma lines for a first time period to operate the gamma line interconnect circuit in a coarse restore mode to reduce a voltage level swing of a victim gamma line (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, frame, line, and dot-inversion disclosed, charge sharing performed for a predetermined period before polarity switch),
and electrically isolate the first to N-th gamma lines from each other for a second time period after the first time period to operate in a fine restore mode to restore a voltage level of the victim gamma line (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, frame, line, and dot-inversion disclosed, charge sharing performed for a predetermined period before polarity switch).
Huang fails to disclose interconnecting the first to N-th gamma lines in response to a change in a gray level value of the source drive circuit to operate the gamma line interconnect circuit in a coarse restore mode to reduce a voltage level swing of a victim gamma line caused by the change in the gray level value.
Lo teaches interconnecting the first to N-th gamma lines in response to a change in a gray level value of the source drive circuit to operate the gamma line interconnect circuit in a coarse restore mode to reduce a voltage level swing of a victim gamma line caused by the change in the gray level value (fig. 12, ¶ 90-100, when display data changes, switches are operated to boost mode to rapidly settle and stabilize the gamma voltages).
Huang and Lo are both directed to gamma voltage generating circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Huang with the device of Lo since such a modification rapidly settles and stabilizes the gamma voltages (Lo, ¶ 93) and reduces power consumption (Lo, ¶ 99).
Regarding claim 13, Huang discloses wherein: the gamma line interconnect circuit comprises: first to N-th switches connected between the first to N-th gamma lines and first to N-th nodes, respectively (fig. 6, ¶ 27, charge-sharing switches 616 controlled by signal S1);
and a resistor string that comprises a first to (N-1)-th resistors connected between pairs of adjacent nodes from among the first to N-th nodes, respectively (¶ 5, fig. 6, ¶ 27, resistor circuit 410).
Regarding claim 14, Lo further teaches wherein: the change in the gray level value occurs at a first time point, and each of the first to N-th switches is configured to: be turned on during the first time period from the first time point to a second time point, and be turned off before the first time point and after the second time point (fig. 12, ¶ 90-100, when display data changes, switches are operated to boost mode to rapidly settle and stabilize the gamma voltages; switches return to first mode after a predetermined period).
Regarding claim 15, Huang discloses wherein: a first resistance-capacitance time constant between the source drive circuit and the gamma voltage generator in the coarse restore mode is less than a second resistance-capacitance time constant between the source drive circuit and the gamma voltage generator in the fine restore mode (figs. 6-7, ¶ 27-30, charge sharing performed for a predetermined period before polarity switch, charge-sharing connects gamma lines in parallel to bypass resistor circuit 410).
Regarding claim 16, Huang discloses wherein: the gamma voltage generator comprises: a first gamma amplifier configured to output a first gamma voltage to a first tap node connected to a first gamma line (fig. 7, ¶ 30, e.g., first buffer 718; see also fig. 9, ¶ 33);
a second gamma amplifier configured to output the N-th gamma voltage to a second tap node connected to the N-th gamma line (fig. 7, ¶ 30, e.g., third buffer 718; see also fig. 9, ¶ 33);
and a divider circuit connected between the first tap node and the second tap node, and configured to output the second to (N-1)-th gamma voltages (fig. 7, ¶ 30, e.g., second buffer 718 connected to V1 divides V0 and V2; see also fig. 9, ¶ 33).
Regarding claim 17, Huang discloses wherein: the first node is connected to the first tap node through a first hold line, and the second node is connected to the second tap node through a second hold line (fig. 7, ¶ 30, e.g., lines connecting buffers 718 to nodes; see also fig. 9, ¶ 33).
Regarding claim 19, Huang discloses a display device comprising: a display panel comprising a first plurality of pixels and a second plurality of pixels (fig. 1, ¶ 5-6, ¶ 9, LCD panel 11 with pixels disclosed);
and a display drive circuit configured to control the first plurality of pixels and the second plurality of pixels (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, source driver 13),
wherein the display drive circuit comprises: a gamma voltage generator providing different gamma voltages to a plurality of gamma lines (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, reference voltage generation circuit 600);
a first source drive circuit array connected with the plurality of gamma lines, and comprising a first plurality of source drive circuits configured to control the first plurality of pixels (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, source driver 13 with corresponding data lines);
a second source drive circuit array connected with the plurality of gamma lines, and comprising a second plurality of source drive circuits configured to control the second plurality of pixels (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, source driver 13 with corresponding data lines);
and a gamma line interconnect circuit located between the first source drive circuit array and the second source drive circuit array, and configured to interconnect the plurality of gamma lines during a predetermined time period to operate the gamma line interconnect circuit in a coarse restore mode to reduce a voltage level swing of a victim gamma line (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, frame, line, and dot-inversion disclosed, charge sharing performed for a predetermined period before polarity switch),
and electrically isolate the plurality of gamma lines from each other after the predetermined time period in a fine restore mode to restore a voltage level of the victim gamma line (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, frame, line, and dot-inversion disclosed, charge sharing performed for a predetermined period before polarity switch).
Huang fails to disclose interconnecting the plurality of gamma lines in response to a change in one or more gray level values of the first plurality of source driver circuits and the second plurality of source drive circuits to operate the gamma line interconnect circuit in a coarse restore mode to reduce a voltage level swing of a victim gamma line caused by the change in the gray level value.
Lo teaches interconnecting the plurality of gamma lines in response to a change in one or more gray level values of the first plurality of source driver circuits and the second plurality of source drive circuits to operate the gamma line interconnect circuit in a coarse restore mode to reduce a voltage level swing of a victim gamma line caused by the change in the gray level value (fig. 12, ¶ 90-100, when display data changes, switches are operated to boost mode to rapidly settle and stabilize the gamma voltages).
Huang and Lo are both directed to gamma voltage generating circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Huang with the device of Lo since such a modification rapidly settles and stabilizes the gamma voltages (Lo, ¶ 93) and reduces power consumption (Lo, ¶ 99).
Regarding claim 20, Huang discloses wherein: the gamma line interconnect circuit comprises: a resistor string; and a plurality of switches respectively connected between one of a plurality of nodes included in the resistor string and one of the plurality of gamma lines (¶ 5-6, fig. 6, ¶ 27, e.g., resistor circuit 410 and charge-sharing switches 616 controlled by signal S1);
and each of the plurality of switches is turned on during a time period from a first time point to a second time point, and turned off before the first time point and after the second time point (fig. 1, ¶ 5-6, ¶ 9, see also figs. 6-7, ¶ 25-30, frame, line, and dot-inversion disclosed, charge sharing performed for a predetermined period before polarity switch).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Lo as applied to claim 16 above, and further in view of Suzuki (US 2008/0100646).
Regarding claim 18, Huang in view of Lo fails to disclose wherein: the gamma voltage generator further comprises: a first dummy gamma amplifier configured to provide a first dummy voltage corresponding to the first gamma voltage to the first node; and a second dummy gamma amplifier configured to provide a second dummy voltage corresponding to the N-th gamma voltage to the N-th node.
Suzuki teaches wherein: the gamma voltage generator further comprises: a first dummy gamma amplifier configured to provide a first dummy voltage corresponding to the first gamma voltage to the first node (figs. 8-9, ¶ 45-50, amplifier 261);
and a second dummy gamma amplifier configured to provide a second dummy voltage corresponding to the N-th gamma voltage to the N-th node (figs. 8-9, ¶ 45-50, amplifier 26m).
Huang in view of Lo and Suzuki are both directed to gamma voltage generating circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Huang in view of Lo with the dummy gamma amplifiers of Suzuki since such a modification stabilizes reference voltages and grayscale voltages (Suzuki, ¶ 50).
Response to Arguments
Applicant’s arguments with respect to claims 1, 12, and 19 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH L CRAWLEY whose telephone number is (571)270-7616. The examiner can normally be reached Monday - Friday 10-6 ET.
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/KEITH L CRAWLEY/Primary Examiner, Art Unit 2626
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