Prosecution Insights
Last updated: April 19, 2026
Application No. 18/387,870

CAPACITIVE BUTTON

Non-Final OA §103§DP
Filed
Nov 08, 2023
Examiner
SAEED, AHMED M
Art Unit
2831
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 2m
To Grant
93%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
597 granted / 737 resolved
+13.0% vs TC avg
Moderate +12% lift
Without
With
+12.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
19 currently pending
Career history
756
Total Applications
across all art units

Statute-Specific Performance

§103
46.3%
+6.3% vs TC avg
§102
47.4%
+7.4% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 737 resolved cases

Office Action

§103 §DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 1, line 4, “arranged more on a back side” lacks an objective boundary and fails to particularly point out the location of the sensor electrode. Claim 2, lines “from a back side” and “from the front side to the back side” lacks an objective reference and render the claim indefinite. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1 and 2 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18286772 in view of Hotelling (US20080007539) and Tanemura (US20190064956). Claim 1 of Application No. 18286772 is similar to the claims 1-2 of the present application (except minor terms difference such reception electrode vs detection electrodes), but missing a mesh shape and the electrode for reception having an area smaller than an area of the electrode for transmission. However, Hoteling teaches an electrode for reception 110 (paragraph 65-67) having an area smaller than an area of the electrode for transmission (Figs. 4-7 and paragraph 66), and Tanemura teaches a sensing electrode 120 which are formed in a mesh shape (see paragraph 59). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Tanemura and Hotelling in order to improve overall sensing performance across different operating conditions. This is a provisional nonstatutory double patenting rejection. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Hotelling (US20080007539) in view of Reynolds (US20090033343) and Tanemura (US20190064956). Regarding claim 1, Hotelling teaches a capacitive button comprising: an operation accepting body 102 which is formed of an insulator (106, 102, see paragraph 65); and a pair of sensor electrodes (110, 108) which are arranged more on a back side than the operation accepting body, wherein one of the pair of sensor electrodes is an electrode for transmission 108 and another one of the pair of sensor electrodes is an electrode for reception 110 (paragraph 65-67) having an area smaller than an area of the electrode for transmission (Figs. 4-7 and paragraph 66). Hotelling does not teach sensor electrodes are formed in a mesh shape. However, Tanemura teaches a similar capacitive device that comprises a sensing electrode 120 which are formed in a mesh shape (see paragraph 59). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Tanemura in order to improve overall sensing performance across different operating conditions. Hotelling does not teach a ground electrode which is arranged so as to surround the operation accepting body, and is grounded. However, Reynolds capacitive device that comprises an operation accepting body (111-115) that is grounded and surrounded by a ground electrode 120 (Fig. 1 and paragraph 19).It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Reynolds in order to reduce parasitic capacitance and noise and thereby improves the reliability of the capacitive device. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hotelling, Reynolds and Tanemura applied to claim 1, and further in view of Kirton (US. Pat. 5,235,217). Regrading claim 3, Hotelling teaches the capacitive button using a pair of electrode (drive electrode 108 and sensing electrode 110) acting as excitation and detection electrodes (paragraphs 47-53); the electrode are connected to a controller and associated circuits including multiplexers, ADCs and signal processors (paragraphs 60-64), which implies electrical circuits for signal processing and control. Hotelling does not explicitly teach connecting the sensor electrode via a resistor and suppressor to a microcomputer, regulator, and regulated power supply in a way to set a characteristic impedance to be electrically uniform with them. However, Kirton teaches a similar capacitive control system wherein the pair of sensor electrodes are connected to a circuit to which a microcomputer (col. 3, lines 65-67), a regulator and a regulated power supply are connected (col. 3, lines 60-65), via a resistor 220 and a suppressor 242 (capacitor as suppressor, see col. 4, lines 1-5), and are set such that a characteristic impedance is electrically uniform with the microcomputer, the regulator and the regulated power supply (the frequency-to-voltage converter and the threshold detector imply impedance control for stable operation, see col. 4, lines 1-67). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the sensing circuit of Hotelling utilizing the teachings of Kirton to include resistors, and suppressor between the sensor electrodes and a circuit comprising a microcomputer, regulator, and regulated power supply to filter unwanted noise and improve circuit reliability and sensing accuracy. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hotelling, Reynolds and Tanemura as applied to claim 1, and further in view of Kirton (US. Pat. 5,235,217) and Shirokawa, et al. (US20090001074). Regrading claim 4, Hotelling teaches the capacitive button using a pair of electrode (drive electrode 108 and sensing electrode 110) acting as excitation and detection electrodes (paragraphs 47-53); the electrode are connected to a controller and associated circuits including multiplexers, ADCs and signal processors (paragraphs 60-64), which implies electrical circuits for signal processing and control. Hotelling does not explicitly teach connecting the sensor electrode via a resistor and suppressor to a microcomputer, regulator, and regulated power supply in a way to set a characteristic impedance to be electrically uniform with them. However, Kirton teaches a similar capacitive control system wherein the pair of sensor electrodes are connected to a circuit to which a microcomputer (col. 3, lines 65-67), a regulator and a regulated power supply are connected (col. 3, lines 60-65), via a resistor 220 and a suppressor 242 (capacitor as suppressor, see col. 4, lines 1-5). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the sensing circuit of Hotelling utilizing the teachings of Kirton to include resistors, and suppressor between the sensor electrodes and a circuit comprising a microcomputer, regulator, and regulated power supply to filter unwanted noise and improve circuit reliability and sensing accuracy. Hotelling does not explicitly teach the bypass capacitor connected at microcomputer’s VCC terminal. However, Shirokawa the use of bypass capacitor and connecting it to microcomputer VCC’s terminal for noise suppression. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the sensing circuit of Hotelling utilizing the teachings of Shirokawa to use a bypass capacitor and connecting it to microcomputer VCC’s terminal for noise suppression. Allowable Subject Matter Claims 2, 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 2, the prior art fails to teach or show, alone or in combination, the claimed capacitive button comprising: a holding body which holds the pair of sensor electrodes and the operation accepting body from a back side; and a tactile switch which is provided on the back side of the holding body, and is pressed when the holding body is moved from the front side to the back side. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AHMED M SAEED whose telephone number is (571)270-7976. The examiner can normally be reached 10-8pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Renee Luebke can be reached at (571) 272-2009. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AHMED M SAEED/ Primary Examiner, Art Unit 2833
Read full office action

Prosecution Timeline

Nov 08, 2023
Application Filed
Dec 14, 2025
Non-Final Rejection — §103, §DP
Feb 27, 2026
Interview Requested
Mar 13, 2026
Examiner Interview Summary
Mar 13, 2026
Applicant Interview (Telephonic)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12596223
LIGHTING KEYBOARD AND BACKLIGHT MODULE THEREOF
2y 5m to grant Granted Apr 07, 2026
Patent 12597572
LAYER-STRUCTURED, OPEN-DESIGN KEYBOARD
2y 5m to grant Granted Apr 07, 2026
Patent 12592348
TERMINAL MODULE
2y 5m to grant Granted Mar 31, 2026
Patent 12587194
CAPACITIVE BUTTON
2y 5m to grant Granted Mar 24, 2026
Patent 12580367
ADJUSTABLE PANEL ASSEMBLY AND ELECTRIC APPLIANCE WITH THE SAME
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
93%
With Interview (+12.4%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 737 resolved cases by this examiner. Grant probability derived from career allow rate.

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