DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 5-7 are objected to because of the following informalities:
Claims 5-7 recites the limitation “the or each thick metal layer” wherein each of these claims are dependent from claim 1, which only recites “a thick metal layer”. Rationally claims 5-7 should recite, “the thick metal layer” because there is not plurality of thick metal layer is addressed in claim 1 to recite “each thick metal”. Which constitutes insufficient antecedent basis for this limitation in the claims.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7 are rejected under 35 U.S.C. 103 as unpatentable over § 103 over Camillo-Castillo et al. (US 2016/0372582 A1, henceforth referred to as Camillo-Castillo) in view of Chevalier et. al. ("High-Speed SiGe BiCMOS Technologies: 120-nm Status and End-of-Roadmap Challenges", SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS, 2007 TOPICAL MEE TING ON, IEEE, Pl, 1 January 2007, pages 18-23)
Claim 1 recites a low noise amplifier (LNA) comprising: (i) an SOI substrate with a BOX layer, wherein said SOI substrate comprises a bulk region within which the BOX layer is removed; (ii) a high-resistance SOI substrate comprising a silicon handle wafer having a resistivity greater than 3 kΩ-cm; (iii) a bipolar transistor located in said bulk region; and (iv) a thick metal layer for connecting to the LNA.
Camillo-Castillo discloses an LNA (§0028, §0039) built on an SOI substrate (10) with a BOX layer (14). The device structure 40 (bipolar transistor) is formed in the semiconductor layer (32) grown within the trench (28) — i.e., in the bulk/massive region where the BOX has been removed. (§0018, §0021, §0025).
Camillo-Castillo discloses the high resistance (HR) silicon handle wafer (16) with a resistivity greater than 1 kΩ-cm. (§0012). The claimed resistivity of greater than 3 kΩ-cm represents a quantitative increase within the range of high-resistance silicon substrates contemplated by Camillo-Castillo.
Differences and Motivation to Combine:
Difference (1) — Resistivity > 3 kΩ-cm: Camillo-Castillo's HR handle wafer has resistivity > 1 kΩ-cm. Increasing the substrate resistivity above 3 kΩ-cm to further reduce substrate losses and improve RF isolation would have been an obvious design choice to a PHOSITA. No unexpected technical effect results from selecting a resistivity above 3 kΩ-cm, as such substrates were commercially available and well-understood to reduce parasitic losses in RF applications.
Difference (2) — Thick metal layer: Camillo-Castillo discloses BEOL processing with contacts and wiring (§0029) but does not specifically describe a "thick" metal layer. Chevalier explicitly teaches the use of thick top metal layers for connecting to amplifier circuits in high-speed BiCMOS technologies (Figure 9 of Chevalier). It would have been obvious to a person having ordinary skill in the art (PHOSITA) to apply Chevalier's thick metal layer interconnection technique to the LNA device of Camillo-Castillo to reduce resistive losses in the RF signal path, as this is a well-known practice in RF integrated circuit design.
Accordingly, claim 1 is rejected under § 103 as obvious over Camillo-Castillo in view of Chevalier.
Claim 2 depends on claim 1 and further specifies that the bipolar transistor is a SiGe transistor.
Camillo-Castillo expressly discloses that the base layer (42) of device structure (40) may be comprised of silicon-germanium (SiGe), making device structure (40) a heterojunction bipolar transistor (HBT) with a SiGe base — i.e., a SiGe transistor. (§0026: "The base layer 42 may be comprised of a semiconductor material, such as silicon-germanium (SiGe)...").
Claim 3 depends on Claim 1 and further recites a plurality of thin metal layers located between the thick metal layer and the SOI substrate.
Chevalier (Figure 9) explicitly illustrates a multilevel metal stack comprising multiple thin metal interconnect layers situated below a thick top metal layer in high-speed SiGe BiCMOS technology. Applying Chevalier's multilayer metal stack to the device of Camillo-Castillo would be an obvious and routine design implementation. The use of multiple thin metal layers for local interconnect, combined with a thick top metal for low-resistance RF connections, is a standard architecture in RF IC back-end processing. A PHOSITA would have had both the motivation and the reasonable expectation of success in implementing this structure in Camillo-Castillo’s LNA.
Claim 4 depends on claim 1 and recites a second thick metal layer vertically displaced from the first thick metal layer so that the thick metal layers are at least partly overlapping.
Chevalier teaches the use of thick metal layers in high-speed BiCMOS technology (Figure 9). The use of multiple vertically staggered thick metal layers in overlapping arrangement to form low-resistance inductors, transmission lines, or shielding structures in RF ICs is a well-known and widely practiced technique in the art at the time of filing. A PHOSITA would have recognized that adding a second thick metal layer in vertical alignment with the first, in the device of Camillo-Castillo as modified by Chevalier, is an obvious design variation to achieve desired electrical properties such as increased inductance, reduced skin effect losses, or improved Q-factor.
Claim 5 depends on Claim 1 and specifies that each thick metal layer comprises copper. Chevalier illustrates thick metal layers in BiCMOS back-end structures. The use of copper as the preferred material for thick metal layers in RF BEOL processes was well-established at the time of filing due to its superior electrical conductivity compared to aluminum. Camillo-Castillo also references metallic conductors such as titanium-nitride-lined tungsten (§0027) in its BEOL processing, demonstrating awareness of advanced metal materials. The selection of copper for the thick metal layer would have been an obvious choice to a PHOSITA seeking to minimize resistive losses in the RF signal path, with no unexpected results.
Claim 6 depends on claim 1 and specifies that each thick metal layer has a thickness greater than 1 µm. Chevalier teaches the use of thick metal layers in SiGe BiCMOS RF technology. A metal layer thickness greater than 1 µm to achieve low sheet resistance for RF applications was a well-known design parameter at the time of filing. The specification of a minimum thickness of 1 µm represents an obvious selection of a suitable range that would have been within the routine design capability of a PHOSITA to optimize RF performance and would not have produced any unexpected result.
Claim 7 depends on claim 1 and specifies that each thick metal layer has a thickness in the range of 2 µm to 4 µm. For the same reasons stated with respect to Claim 6, the specification of a thickness range of 2 µm to 4 µm represents a routine optimization of the thick metal layer thickness. Chevalier teaches thick metal layers for RF applications. The narrowing of this range to 2–4 µm is a predictable selection of parameters that a PHOSITA would make through routine experimentation to balance low resistivity against process constraints such as planarization and stress. No unexpected results arise from this selection.
Claims 8-17 are rejected under 35 U.S.C. 103 as unpatentable over § 103 over Camillo-Castillo in view of Chevalier and further in view of Jain et. al. (US 20190081597 A1).
Claim 8 depends on claim 1 and further specifies that the LNA comprises a cascode structure and the bipolar transistor is a common emitter of said cascode structure.
Camillo-Castillo discloses an LNA structure using a BJT device (§0028, §0039). Vibhor discloses cascode amplifier structures employing bipolar transistors on SOI substrates, with the bipolar transistor configured as the common emitter stage of the cascode (see §0019–§0040 of Jain, Figures 1–10). The use of a cascode topology in LNAs to achieve high gain, improved reverse isolation, and reduced Miller effect was a widely established circuit design technique at the time of filing. A PHOSITA would have been motivated to implement the LNA of Camillo-Castillo (as modified by Chevalier) in a cascode configuration as taught by Jain, with a reasonable expectation of achieving the known performance advantages of cascode LNAs in wireless receiver applications.
Claim 9 depends on claim 8 and further recites that the LNA comprises a second bipolar transistor arranged to form a common base of the cascode structure.
Jain discloses a cascode amplifier structure comprising a first bipolar transistor (common emitter) and a second bipolar transistor configured as the common base stage of the cascode (see Figures 1–10, §0019–§0040). Implementing a BiCMOS cascode LNA with a second bipolar transistor in the common base configuration, as taught by Jain, applied to the device of Camillo-Castillo modified by Chevalier, would have been obvious to a PHOSITA. Using a bipolar transistor in the common base position of a cascode LNA was a standard circuit technique to maximize bandwidth and reduce noise figure in RF applications at the time of filing.
Claim 10 depends on claim 8 and further recites that the LNA further comprises a SOI transistor arranged to form a common gate of the cascode structure.
Jain discloses amplifier structures on SOI substrates utilizing SOI FETs in various circuit configurations. The use of a SOI transistor (field-effect transistor) in the common gate position of a cascode structure is taught by Jain (see Figure 4, §0019–§0040). Substituting or adding a SOI transistor as the common gate element in the cascode LNA of Camillo-Castillo as modified by Chevalier and Jain would have been an obvious circuit design choice to a PHOSITA seeking to leverage the low parasitic capacitance and excellent isolation properties of SOI FETs for high-frequency amplification. The French Written Opinion specifically noted that claims 10 and 11 are described in Jain at Figure 4.
Claim 11 depends on claim 10 and specifies that the SOI transistor is a complementary metal-oxide semiconductor (CMOS) transistor.
Jain discloses SOI transistors in the context of mixed BiCMOS architectures (§0019–§0040). CMOS transistors fabricated on SOI substrates were well-known and widely used in RF circuit applications at the time of filing. Specifying that the SOI transistor of Claim 10 is a CMOS transistor represents an obvious selection of a well-known device type that is commonly available in BiCMOS SOI technology platforms such as that disclosed in Camillo-Castillo, Chevalier, and Jain. No unexpected results arise from this limitation.
Claim 12 depends on claim 1 and recites that the LNA comprises a first stage amplifying circuit and a second stage amplifying circuit, wherein the first stage amplifying circuit comprises the bipolar transistor and the second stage amplifying circuit comprises a cascode structure.
Jain discloses multi-stage amplification circuits comprising a first amplifying stage including a bipolar transistor and a second stage employing a cascode structure, on an SOI substrate (see Figures 1–10, §0019–§0040). A two-stage LNA architecture with a bipolar first stage (for low noise) followed by a cascode second stage (for gain and isolation) was a well-known and commonly practiced approach in RF IC design at the time of filing. A PHOSITA would have been motivated to implement the LNA of Camillo-Castillo (as modified by Chevalier) in the two-stage architecture taught by Jain to achieve improved overall LNA performance.
Claim 13 depends on claim 12 and specifies that the cascode structure of the second stage comprises a first SOI transistor being a common source and a second SOI transistor being a common gate of the cascode structure.
Jain discloses cascode structures utilizing SOI transistors in common-source/common-gate configurations on SOI substrates (see Figure 4). The use of a fully SOI FET-based cascode (common source + common gate) in the second stage of a two-stage LNA, combined with the bipolar first stage of Camillo-Castillo as modified by Chevalier, represents an obvious combination of known circuit elements. A PHOSITA would have recognized the performance benefits of an all-FET cascode second stage for achieving high output impedance and gain and would have implemented this architecture with a reasonable expectation of success.
Claim 14 depends on claim 12 and recites that the cascode structure comprises a second bipolar transistor in a bulk region of the SOI substrate as the common emitter, and a SOI transistor as the common gate.
Jain teaches cascode amplifier structures on SOI substrates combining bipolar transistors (in bulk regions) with SOI FETs (see Figures 1–4 and related description, §0019–§0040). A mixed BiCMOS cascode structure using a bipolar transistor as the common emitter and an SOI FET as the common gate in the second stage of an LNA was a known circuit topology in the art. This configuration is a straightforward application of the circuit techniques of Jain to the device structure of Camillo-Castillo as modified by Chevalier would have been obvious to a PHOSITA.
Claim 15 depends on claim 12 and recites that the first stage amplifying circuit further comprises a second cascode structure comprising the bipolar transistor as the common emitter of said second cascode structure.
Jain discloses cascode LNA topologies including those where the first amplification stage itself is implemented as a cascode structure with a bipolar transistor as the common emitter (see Figures 1–10, §0019–§0040). Implementing a cascode topology in the first stage (rather than a single-transistor common emitter stage) to achieve higher gain and better isolation is an obvious design variation that a PHOSITA would consider. Jain teaches this configuration in the context of SOI-based amplifiers and applying it to the device of Camillo-Castillo as modified by Chevalier would be an obvious implementation choice.
Claim 16 depends on claim 15 and recites that the second cascode structure comprises a second bipolar transistor in a bulk region of the SOI substrate, wherein the second bipolar transistor is a common base of the cascode structure.
This limitation mirrors the configuration of Claim 9 (bipolar transistor as common base) applied to the first-stage cascode structure. As discussed for Claims 9 and 15, Jain teaches cascode amplifier structures on SOI substrates with bipolar transistors in common base configuration (see Figures 1–10, §0019–§0040). Applying this teaching to the first-stage cascode of Claim 15 is an obvious extension of the reasoning provided for Claims 9 and 15.
Claim 17 depends on claim 15 and recites that the second cascode structure comprises a SOI transistor as the common gate. This limitation is the direct analog of Claim 10 (SOI transistor as common gate) applied to the first-stage cascode. Jain discloses SOI transistors in the common gate position of cascode structures on SOI substrates (Figure 4, §0019–§0040). For the same reasons stated with respect to Claims 10 and 15, this configuration would have been obvious to a PHOSITA, representing a straightforward application of well-known cascode circuit topologies using available device types in BiCMOS SOI technology.
Claims 18 is rejected under 35 U.S.C. 103 as unpatentable over § 103 over Camillo-Castillo.
Claim 18 depends on claim 1 and recites an apparatus for telecommunications comprising the LNA, wherein the LNA is arranged in the apparatus to amplify a signal received by the apparatus.
Camillo-Castillo expressly discloses that bipolar junction transistors may find specific end uses in amplifiers for wireless communications systems and mobile devices (§0002). Camillo-Castillo further discloses that the LNA device may be used in wireless communication applications (§0002, §0028, §0039). Incorporating the LNA of Claim 1 (as modified) into a telecommunications apparatus to amplify received signals is the intended use of the claimed LNA was expressly contemplated by Camillo-Castillo. This limitation adds no patentable weight, and the claim is rejected under § 103 as obvious over Camillo-Castillo for the same reasons stated for Claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.