DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s Admitted Prior Art; i.e., Van den Dool et al. (“Indirect current feedback instrumentation amplifier with a common-mode input range that includes the negative roll,” IEEE Journal of Solid-State Circuits, vol. 28, no. 7, pp. 743-749, 1993) in view of Gerfers et al. (US 2022/0407539).
Regarding claim 1, Applicant’s Admitted Prior Art, as depicted in Fig. 3b of the instant application, discloses a monolithically-integrated current-feedback instrumentation amplifier comprising: a first differential pair of transistors (M1, M2) configured for receiving a differential input signal (Vin+,Vin-) on gate or base terminals of said transistors (M1, M2) (see Fig. 3b); a second differential pair of transistors (M3, M4) configured for receiving a differential feedback signal (Vfb+, Vfb-) on gate or base terminals of said transistors (M3, M4) (see Fig. 3b); wherein a drain or collector terminal of a first transistor (M1) of the first differential pair (M1, M2) is directly connected to a drain or collector terminal of a first transistor (M3) of the second differential pair (M3, M4) and to a non-inverting, high-impedance input terminal of a differential voltage amplifier (see Fig. 3b), and is connected to a ground terminal by means of a first sink resistor (Rsink) (see Fig. 3b); and a drain or collector terminal of a second transistor (M2) of the first differential pair (M1, M2) is directly connected to a drain or collector terminal of a second transistor (M4) of the second differential pair (M3, M4) and to an inverting, high-impedance input terminal of the differential voltage amplifier (see Fig. 3b), and is connected to a ground terminal by means of a second sink resistor (Rsink) (see Fig. 3b); and wherein an output terminal of the differential voltage amplifier, serving as an output terminal of the current-feedback instrumentation amplifier, is connected to a resistive voltage divider providing said differential feedback signal (Vfb+, Vfb-) (see Fig. 3b).
Although the Applicant’s Admitted Prior Art does not disclose the source or emitter terminals of the transistors of the first differential pair (M1, M2) being directly connected together without a degeneration resistor, Gerfers et al. shows that this feature is well known in the art. Gerfers et al. discloses a transconductance amplifier (element 11, Fig. 14), wherein source or emitter terminals of the transistors of the first differential pair (elements T1, T2, Fig. 14) are directly connected together and to a first bias current source without a degeneration resistor (see Fig. 14), and source or emitter terminals of the transistors of the second differential pair (elements T3, T4, Fig. 14) are directly connected together and to a second bias current source (see Fig. 14) also without a degeneration resistor. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to apply a known technique to a known device ready for improvement to yield predictable results, such as achieving a high signal-to-noise ratio (SNR) and high linearity with minimal power dissipation as taught by Gerfers et al. (see par. [0010]).
Regarding claim 2, Applicant’s Admitted Prior Art, wherein the resistive voltage divider is connected between said output terminal of the differential voltage amplifier and a reference voltage terminal (see Fig. 3b).
Regarding claim 3, although the Applicant’s Admitted Prior Art does not disclose the reference voltage terminal is kept at a potential substantially equal to half a supply voltage of the first and second current sources and of the differential voltage amplifier, the applicant did not traverse the examiner’s assertion of official notice, the examiner is hereby indicating that the common knowledge or well-known in the art statement is taken to be admitted prior art because applicant failed to traverse the examiner’s assertion of official notice. Therefore, determining the optimum or workable value of reference potential is not an inventive limitation, since it could be determined by one with ordinary skill in the art through routine experimentation as a matter of obvious design choice for the desired practical application.
Regarding claim 4, Applicant’s Admitted Prior Art, wherein the feedback signal is acquired across a gain resistor (R4) of the resistive voltage divider (see Fig. 3b).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s Admitted Prior Art in view of Gerfers et al. (US 2022/0407539) as applied to claims 1-4 above, and further in view of Gadola et al. (“1.3 mm2 nav-grade nems-based gyroscope,” Journal of Microelectromechanical Systems, vol. 30, no. 4, pp. 513-520, 2021).
Regarding claims 8-10, although the Applicant’s Admitted Prior Art does not disclose a sensing system comprising a piezoresistive NEMS or MEMS sensor and a monolithically-integrated differential readout circuit, Gadola et al. shows that this feature is well known in the art. Gadola et al. discloses a sensing system comprising a piezoresistive NEMS or MEMS sensor and a monolithically-integrated differential readout circuit (see Fig. 4), wherein the differential readout circuit comprises, as a front-end amplifier (see Fig. 4), the current-feedback instrumentation amplifier, wherein the piezoresistive NEMS or MEMS sensor comprises a pair of piezoresistive gauges whose resistance value changes by opposite amounts upon application of a stimulus to the sensor (see Fig. 4), said piezoresistive gauges being electrically connected to each other and to a reference voltage terminal and belonging to different legs of a Wheatstone bridge (see Fig. 4), the gate or base terminals of the first differential pair of transistors of the current-feedback instrumentation amplifier being connected to respective midpoints of said legs (see Fig. 4), wherein the piezoresistive NEMS or MEMS sensor is a Coriolis vibratory gyroscope (see Fig. 4). Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to apply a known technique to a known device ready for improvement to yield predictable results, such as providing a high precision readout of the measured values.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Huijsing et al. (US 6,559,720) discloses a GM-controlled current-isolated indirect-feedback instrumentation amplifier.
Allowable Subject Matter
No art has been found for a prior art rejection of claims 5-7 and 11 at this time.
Response to Arguments
Applicant's arguments filed 4/1/2026 have been fully considered but they are not persuasive.
The applicant argues that “one of ordinary skill in the art starting from Van den Dool would have no reason to remove the degeneration resistors based on Gerfers, because doing so would undermine the very stability that Van den Dool seeks to achieve”. The examiner respectfully disagrees. Gerfers et al. recognizes that devices including a degeneration resistor have a very high thermal noise and then provides an alternative solution that achieves a high signal-to-noise ratio (SNR) and high linearity with minimal power dissipation.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the applicant’s finding that the reduction in part-to-part repeatability resulting from the suppression of source degeneration resistors can be made negligible through proper sizing, so that the two monolithically co-integrated transistors are very close to each other) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In response to applicant's argument that Gerfers and Van den Dool are non-analogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, Gerfers et al. is clearly pertinent to the particular problem of the degeneration resistor leading to very high thermal noise.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MILTON GONZALEZ whose telephone number is (571)270-7914. The examiner can normally be reached 8:00 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WALTER LINDSAY can be reached at (571) 272-1674. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WALTER L LINDSAY JR/Supervisory Patent Examiner, Art Unit 2852
/M.G/Examiner, Art Unit 2852
6/14/2026
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