DETAILED ACTION
This non-final action replies to application, filed Nov. 9, 2023, that is a broadening reissue application of 16/660846, now U.S. Pat. 11,736,313 with a co-filed amendment that amends claims 1, 4, 5 and adds new claims 8-11. Claims 1-11 are pending. This application is deemed a reissue of 11,171,804 due to indications in the filed Reissue Patent Application Transmittal, Consent of Assignee, Reissue Application Declaration by Assignee with associated error statement that state this is a reissue of 11,171,804 (as copied elsewhere herein).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Data Sheet (ADS)
The Application Data Sheet (ADS) co-filed with application on 11/9/2023 is objected to under 37 CFR 1.76 for inconsistent designation that this reissue application is a reissue of 11,736,313 rather than a reissue of 11,171,804. Notably, the current ADS indicates this is a reissue of 11,736,313 where if this application is a reissue of 11,736,313 then this issue is moot. However, based on other above noted indications by Applicant, this is a reissue of 11,171,804. For instance, the two ADS, filed 11/9/2023 ADS and 11/10/2023, by Applicant indicate this application is a reissue of 11,736,313, as shown next; thus, the ADS provides an incorrect indication this is a reissue of 11,736,313 that is inconsistent with other filed documents.
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Reissue Application Declaration and 35 USC 251
The reissue application declaration by assignee, filed on Nov. 9, 2023, for this application is defective because it conflicts as to which patent is under reissue. See 37 CFR 1.175 and MPEP § 1414. A reissue application declaration by the assignee (PTO/AIA /06) is defective for the situation where this is a reissue of 11,171,804 (not applicable if this is a reissue of 11,736,313 as indicated in noted ADS), since the error statement regards an impermissible error, in this case, as relying on an error regarding omission of surrendered subject matter in 16/660846, as further detailed in improper recapture below relied on herein. As shown in copied text of error statement below, the “wherein” clause between points of the two arrows in copied text from reissue error statement regards the surrendered subject matter from original claim 14 added to claim 1 in amendment filed June 23, 2021 that Applicant concurrently stated “Claim 1 is amended… Claim 1 is amended to include the limitations of allowable claim 14. Therefore claim 1 is believed to be allowable.”.
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The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. §251 that form the basis for the rejections under this section made in this Office action:
(a) IN GENERAL.—Whenever any patent is, through error, deemed wholly or partly inoperative or invalid, by reason of a defective specification or drawing, or by reason of the patentee claiming more or less than he had a right to claim in the patent, the Director shall, on the surrender of such patent and the payment of the fee required by law, reissue the patent for the invention disclosed in the original patent, and in accordance with a new and amended application, for the unexpired part of the term of the original patent. No new matter shall be introduced into the application for reissue.
Claims 1-11 are rejected as being based upon a defective reissue application declaration by the inventor under 35 U.S.C. 251 as set forth above. See 37 CFR 1.175. The nature of the defect(s) in the declaration is set forth in the discussion above in this Office action. See 37 CFR 1.175 and MPEP § 1414. MPEP 1414 II.(B) states in part: “In identifying the error, it is sufficient that the reissue oath/declaration identify a single word, phrase, or expression in the specification or in an original patent claim, and how it renders the original patent wholly or partly inoperative or invalid.” The error statement in the co-filed declaration refers to a limitation of claim 1 of 11,171,804 but the ADS cites this is a reissue of 11,736,313. Also, the limitation of claim 1 of 11,171,804 stated as being omitted in the error statement for claim 1 herein regards an impermissible error for reasons noted herein and in improper recapture discussion below. See MPEP 1414 II. (C). See 37 CFR 1.175 and MPEP § 1414. See In re Tanaka, 640 F.3d 1246, 1251, 98 USPQ2d 1331, 1334 (Fed. Cir. 2011).
Claims 1-11 are rejected under 35 U.S.C. 251 as being an improper recapture of broadened claimed subject matter surrendered in the application for the patent upon which the present reissue is based. See Greenliant Systems, Inc. et al v. Xicor LLC, 692 F.3d 1261, 103 USPQ2d 1951 (Fed. Cir. 2012); In re Shahram Mostafazadeh and Joseph O. Smith, 643 F.3d 1353, 98 USPQ2d 1639 (Fed. Cir. 2011); North American Container, Inc. v. Plastipak Packaging, Inc., 415 F.3d 1335, 75 USPQ2d 1545 (Fed. Cir. 2005); Pannu v. Storz Instruments Inc., 258 F.3d 1366, 59 USPQ2d 1597 (Fed. Cir. 2001); Hester Industries, Inc. v. Stein, Inc., 142 F.3d 1472, 46 USPQ2d 1641 (Fed. Cir. 1998); In re Clement, 131 F.3d 1464, 45 USPQ2d 1161 (Fed. Cir. 1997); Ball Corp. v. United States, 729 F.2d 1429, 1436, 221 USPQ 289, 295 (Fed. Cir. 1984). A broadening aspect is present in the reissue which was not present in the application for patent. The record of the application for the patent shows that the broadening aspect (in the reissue) relates to claimed subject matter that applicant previously surrendered during the prosecution of the application (e.g. surrender-generating limitation). Accordingly, the narrow scope of the claims in the patent was not an error within the meaning of 35 U.S.C. 251, and the broader scope of claim subject matter surrendered in the application for the patent cannot be recaptured by the filing of the present reissue application.
Below are the pertinent findings of fact relevant to this rejection:
10/23/2019
The 16/660,846 application (hereafter the ‘846 application) was filed with 1 claim.
04/14/2021
A first official non-final action on the merits was mailed rejecting the claims 1, 4-13, and 15-20 as obvious over US 2017/0010329 (hereinafter Tang), in view of US 7,362,779 (hereinafter Zabezhinsky), rejecting claims 2-3 as obvious US 2017/0010329 (hereinafter Tang), in view of US 7,362,779 (hereinafter Zabezhinsky) and further in view of US 2001/0012692 (hereinafter Miller), and objecting to claim 14 as dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 14 recites “The circuit of claim 12, wherein the association between of the selected downstream node and the respective upstream frame of the upstream aggregate frame is indicated by a time of reception by the downstream port of the respective upstream frame.” (Emphasis added).
06/23/2021
Applicant filed an amendment/reply to amend claim 1 to add limitations of claim 14 and to cancel claims 8-20. On pages 2 and 8, applicant amends claim 1 and states “Claim 1 is amended to include the limitations of allowable claim 14. Therefore claim 1 is believed to be allowable.” As noted, claim 1 was amended to add “wherein the association between of the selected downstream node and the respective upstream frame of the upstream aggregate frame is indicated by a time of reception by the downstream port of the respective upstream frame.” (Emphasis added).
07/08/2021
An allowability notice was mailed with reasons for allowance stating: “The Examiner has conducted a search of Patent and Non-Patent Literature and considered the claims as amended, reaching the determination that the prior objected claim limitations of now cancelled claim 14 in combination with the parent independent claim including all the intervening claims is not explicitly disclosed by any of the prior art resulting from the Examiner's search nor is it disclosed, suggested, taught, or obvious based on any of the Examiner's search yielded prior art in combination; as none of the prior art taught the physical structure layout of the various local controllers, their respective inputs and local buses, in combination with the system bus controller and translator which operate to selectively process aggregate frames between devices based on the timing information, in combination with the other limitations.”
A reissue will not be granted to "recapture" claimed subject matter which was surrendered in an application to obtain the original patent. See MPEP §1412.20. A three step process is used to apply the recapture rule:
(1) first, we determine whether, and in what respect, the reissue claims are broader in scope than the original patent claims;
(2) next, we determine whether the broader aspects of the reissue claims relate to subject matter surrendered in the original prosecution; and
(3) finally, we determine whether the reissue claims were materially narrowed in other respects, so that the claims may not have been enlarged, and hence avoid the recapture rule.” See MPEP §1412.02(I).
The first step of the three-step process we determine whether, and in what respect, the reissue claims are broader in scope than the original patent claims. Upon review of the new independent claim 1 of the present reissue application in comparison to claims 1-7 of ‘804 Patent, the Examiner finds that the Applicant through the Nov. 9, 2023 Amendment herein has broadened the claims by omitting the following limitations in claim 1: “and adapted to receive a first local bus transmission via the first local bus”, “and adapted to receive a second local bus transmission via the second local bus”, “generate a first downstream frame responsive to the first local bus transmission, the system bus controller configured to generate a second downstream frame responsive to the second local bus transmission, the system bus controller configured to generate a downstream aggregate frame responsive to the first downstream frame and the second downstream frame, the system bus controller configured to initiate transmission of the downstream aggregate frame at the downstream port, the system bus controller adapted to” and “wherein the association between of the selected downstream node and the respective upstream frame of the upstream aggregate frame is indicated by a time of reception by the downstream port of the respective upstream frame”, as similarly shown in table next (italicized text in table is omitted language herein as compared to limitations in ‘804). Although the comparison in table regards claim 1 herein, new claim 9 also omits the bolded limitation.
Claim 1, as amended on 11/9/2023, herein
Claim 1 of 11,736,313
A circuit, comprising:
A circuit, comprising:
a first local controller having a first upstream port adapted to be coupled to a first local bus,
the first local controller configured to transmit a first upstream transmission via the first upstream port;
a first local controller having a first upstream port adapted to be coupled to a first local bus and adapted to receive a first local bus transmission via the first local bus, and the first local controller configured to transmit a first upstream transmission via the first upstream port;
a second local controller having a second upstream port adapted to be coupled to a second local bus,
the second local controller configured to transmit a second upstream transmission via the second upstream port;
a second local controller having a second upstream port adapted to be coupled to a second local bus and adapted to receive a second local bus transmission via the second local bus, and the second local controller configured to transmit a second upstream transmission via the second upstream port;
a system bus controller having a downstream port adapted to be coupled to a system bus, the system bus controller configured to
receive an upstream aggregate frame that includes a first upstream frame and a second upstream frame, the system bus controller configured to generate the first upstream transmission responsive to the first upstream frame, and the system bus controller configured to generate the second upstream transmission responsive to the second upstream frame; and
a translator having an input coupled to the downstream port and an output selectively coupled to one of the first upstream port and the second upstream port, the output of the translator selected responsive to an indication of an association between a selected downstream node and a respective upstream frame of the upstream aggregate frame.
and a system bus controller having a downstream port adapted to be coupled to a system bus, the system bus controller configured to generate a first downstream frame responsive to the first local bus transmission, the system bus controller configured to generate a second downstream frame responsive to the second local bus transmission, the system bus controller configured to generate a downstream aggregate frame responsive to the first downstream frame and the second downstream frame, the system bus controller configured to initiate transmission of the downstream aggregate frame at the downstream port, the system bus controller adapted to
receive an upstream aggregate frame that includes a first upstream frame and a second upstream frame, the system bus controller configured to generate the first upstream transmission responsive to the first upstream frame, and the system bus controller configured to generate the second upstream transmission responsive to the second upstream frame; and
a translator having an input coupled to the downstream port and an output selectively coupled to one of the first upstream port and the second upstream port, the output of the translator selected responsive to an indication of an association between a selected downstream node and a respective upstream frame of the upstream aggregate frame; wherein the association between of the selected downstream node and the respective upstream frame of the upstream aggregate frame is indicated by a time of reception by the downstream port of the respective upstream frame.
Regarding step 2, Examiner finds that some of the broadening aspects relate to subject matter surrendered during prosecution of the 16/660846 Application leading to the original claims of ‘804 Patent. The Examiner finds that the Applicant through their Nov. 09, 2023 Amendment in this reissue has broadened the claims by omitting a limitation relating to the surrendered subject matter during examination of the ‘846 application as now particularly recited, that regards language amended into independent claim 1 and concurrently argued by Applicant in the reply filed June 23, 2023 amendment in 16/660846. As noted above in the findings of fact, the Examiner stated reason for allowance allowed certain claims because the prior art of record do not disclose the added/argued limitation of claim 14 that was subsequently incorporated into independent claim 1 in the noted June 2023 amendment during examination of ‘846 Application as present in issued claims 1-7 in ‘804 patent. It is emphasized that Applicant incorporated this limitation and concurrently argued in their response that the added limitation relating to the now omitted feature with consideration of the Comparison of claim 1 herein as compared to issued claim 1 in ‘804 Patent) were a distinguishing limitation over the applied art (e.g., a surrender-generating limitation). As noted above, Applicant argued this feature in their response/amendment during examination. Thus, the noted limitation “wherein the association between of the selected downstream node and the respective upstream frame of the upstream aggregate frame is indicated by a time of reception by the downstream port of the respective upstream frame” in issued claims 1-7 in ‘804 regards subject matter surrendered during prosecution of the '846 Application leading to the original ‘804 Patent. From prosecution of ‘846 Application, the noted limitation regarding surrendered subject matter must be recited in present claims to avoid improper recapture.
Regarding step 3, Examiner further determines there is/are no narrowing limitation(s) herein as compared to ‘804 claims that materially narrow the surrendered subject matter such that they are not directed to the surrendered subject matter.
Thus, in summary, the Examiner specifically finds that the claim 1 (and its dependent claims) have eliminated a feature/limitation through amendment in this application for which the claims of the original Patent were allowed. The Nov. 2023 Amendment herein attempts to improperly recapture surrendered subject matter explicitly surrendered during prosecution of ‘846 Application leading to the ‘804 Patent since an amended/argued limitation during examination of ‘846 Application is eliminated in this reissue application that coincidently regards subject matter relied on during prosecution of parent application to obtain the original patent. Claim scope that was canceled or amended is deemed surrendered and therefore barred from reissue. Clement, 131 F.3d at 1470, 45 USPQ2d at 1165. In re Mostafazadeh, 98 USPQ2d 1639 (Fed Cir 2011), In re Youman, 102 USPQ2d 1862 (Fed Cir 2012). Next, there is no narrowing feature added by the preliminary amendment herein that materially narrows relative to the surrender-generating limitation. Specifically, independent claims 1 and 9 (and their associated dependent claims) herein have omitted the feature “wherein the association between of the selected downstream node and the respective upstream frame of the upstream aggregate frame is indicated by a time of reception by the downstream port of the respective upstream frame” as recited in issued claims 1-7 of ’804. While to the extent there is/are added or narrowed element(s) herein that are not present in ‘804 claims, those element(s) is/are not directed to the noted surrendered subject matter. If surrendered subject matter has been entirely eliminated from a claim present in the reissue application, then a recapture rejection under 35 U.S.C. 251 is proper and must be made for that claim. See MPEP 1412.02 (I)(C). Stated another way, if a claim limitation present in the original patent that was added to overcome a rejection or that was argued by applicant to distinguish over the prior art is entirely eliminated from a claim in the reissue application, then a recapture rejection under 35 U.S.C. 251 is proper and must be made for that claim. See Id.
In view of the forgoing, the Applicant has attempted in the Nov. 2023 Amendment herein to improperly recapture subject matter explicitly surrendered during prosecution of the ‘846 Application leading to the ‘804 Patent for reasons stated above.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 and 9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 11,736,313 in view of U.S. Pat. App. No. 2018/0060269 (hereinafter Kessler) or U.S. Pat. App. No. US 2001/0012692 (hereinafter Miller). Lacking evidence to the contrary, with broadest reasonable interpretation of the claims without reading limitations from disclosure of ‘804 into the claims herein, although the claims at issue are not identical, they are not patentably distinct from each other for the following reason: in comparing Claims 1-8 of U.S. 11736313 to Claim 1of the instant application (hereinafter IA), the Claims 1-8 of U.S. 11736313 are an obvious variant that contain substantially the same subject matter that overlaps Circuit of IA as shown in table next (italicized text in ‘313 is omitted in claim 1 herein).
Claim 1, as amended on 11/9/2023, herein
Claim 1 of 11,736,313
A circuit, comprising:
A circuit, comprising:
a first local controller having a first upstream port adapted to be coupled to a first local bus,
the first local controller configured to transmit a first upstream transmission via the first upstream port;
a first local controller having a first upstream port adapted to be coupled to a first local bus and adapted to receive a first local bus transmission via the first local bus, and the first local controller configured to transmit a first upstream transmission via the first upstream port;
a second local controller having a second upstream port adapted to be coupled to a second local bus,
the second local controller configured to transmit a second upstream transmission via the second upstream port;
a second local controller having a second upstream port adapted to be coupled to a second local bus and adapted to receive a second local bus transmission via the second local bus, and the second local controller configured to transmit a second upstream transmission via the second upstream port;
a system bus controller having a downstream port adapted to be coupled to a system bus, the system bus controller configured to
receive an upstream aggregate frame that includes a first upstream frame and a second upstream frame, the system bus controller configured to generate the first upstream transmission responsive to the first upstream frame, and the system bus controller configured to generate the second upstream transmission responsive to the second upstream frame;
and
a translator having an input coupled to the downstream port and an output selectively coupled to one of the first upstream port and the second upstream port, the output of the translator selected responsive to an indication of an association between a selected downstream node and a respective upstream frame of the upstream aggregate frame.
and a system bus controller having a downstream port adapted to be coupled to a system bus, the system bus controller configured to generate a first downstream frame responsive to the first local bus transmission, the system bus controller configured to generate a second downstream frame responsive to the second local bus transmission, the system bus controller configured to generate a downstream aggregate frame responsive to the first downstream frame and the second downstream frame, the system bus controller configured to initiate transmission of the downstream aggregate frame at the downstream port, the system bus controller adapted to
receive an upstream aggregate frame that includes a first upstream frame and a second upstream frame, the system bus controller configured to generate the first upstream transmission responsive to the first upstream frame, and the system bus controller configured to generate the second upstream transmission responsive to the second upstream frame;
further comprising
a translator having an input coupled to the downstream port and an output selectively coupled to one of the first upstream port and the second upstream port, the output of the translator selected responsive to an indication of an association between a selected downstream node and a respective upstream frame of the upstream aggregate frame.
In general, Claims 1-8 of U.S. 11736313 are an obvious variant of or an overlap of the Circuit of claims herein that similarly recite a first local controller, a second local controller, a system bus controller and a translator. Regarding claim 1 of the IA, claim 1 of Patent ‘313 similarly claims all features as recited herein where the only difference lies in omitted text italicized above. The omitted elements in the claims of IA while leaving all other claimed features the same creates an obvious variation between the claims whereby the claim of the IA is contained within/overlapped by the corresponding claim of ‘313.
Also, the third controller in claim 9 herein is “a system bus controller” in claims of ‘313 where for similar reasons as claim 1 herein as shown in table above, claim 9 herein is obvious variant of claims 1-8 of ‘313 that similarly recite a first local controller, a second local controller, a system bus controller performing similar/same process.
Claims 4-8 and 10-11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 11,736,313 in view of U.S. Pat. No. 7,362,779 (hereinafter Zabezhinsky). Lacking evidence to the contrary, with broadest reasonable interpretation of the claims without reading limitations from disclosure of ‘804 into the claims herein, although the claims at issue are not identical, they are not patentably distinct from each other for the following reason: in comparing Claims 1-8 of U.S. 11736313 to Claims of the instant application, the Claims 1-8 of U.S. 11736313 are an obvious variant that contain substantially the same subject matter that overlaps Circuit herein as shown in table next (italicized text in ‘313 is omitted in claim 1 herein) for reasons above and as discussed next.
Regarding claim 4 herein, the claims of ‘313 lack “a buffer” as recited herein. However, related reference Zabezhinsky teaches a circuit comprising a buffer having an input coupled to the first upstream port and an output coupled to the downstream port, the buffer configured to store an indication of data responsive to the first local bus transmission (the Figure 8, Element 818 indicates that the subframe data may be received and buffered before being input or output amongst the upstream and downstream ports of the channels (specifically the first channel) [Zabezhinsky, 9:1-19]), wherein the system bus controller is configured to generate the first downstream frame responsive to the indication of data (the indicated received data corresponding to each of the channels when buffered may be generated into a data payload from shown in row 1 of Figure 1 for the downstream frame [Zabezhinsky, 3:14-20, 4:13-43]).
Zabezhinsky is deemed herein to be relevant prior art due to either being in the same field of endeavor or being reasonably pertinent to the particular problem with which the Applicant was faced. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). The level of ordinary skill in the art is shown by the applied art herein. Since claims of ‘313 and Zabezhinsky each regard a circuit, in consideration consistent with US Supreme Court decision in KSR that ‘known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art’, in this case, it would have been obvious to an artisan to add “a buffer having an input coupled to the first upstream port and an output coupled to the downstream port, the buffer configured to store an indication of data responsive to a first local bus transmission received at the first upstream port, wherein the system bus controller is configured to generate an aggregate frame including a first downstream frame generated responsive to the indication of data, wherein the system bus controller is configured to provide the aggregate frame at the downstream port” as taught by Zabezhinsky to improve the circuit in claims of ’313 with the motivation to enable indicating that the devices communicate data along their respective channels to a controller or hub that has the ability to receive, store the incoming date and then create subframe/payload data and aggregate these subframes/payload data of the respective channels into an aggregate frame for transmission over a connection. The result would have been to increase performance of the communication of multiple devices over a shared link at high speeds.
Regarding claim 5 herein, the claims of ’313 lack “the buffer” as recited. But, related reference Zabezhinsky teaches a circuit wherein the buffer is a first buffer and the indication of data is a first indication of data, and further comprising a second buffer having an input coupled to the second upstream port and an output coupled to the downstream port, the second buffer configured to store a second indication of data responsive to a second local bus transmission (the Figure 8, Element 818 indicates that the subframe data may be received associated with each of the corresponding channels and buffered before being input or output amongst the upstream and downstream ports of the channels [Zabezhinsky, 9:1-19]) received at the second upstream port, wherein the system bus controller is configured to generate a second downstream frame of the aggregate frame, responsive to the second indication of data (the indicated received data corresponding to each of the channels when buffered may be generated into a data payload from shown in row 1 of Figure 1 for the downstream frame [Zabezhinsky, 3:14-20 and 4:13-43]).
Similar rationale/motivation to combine claims of ’313 and Zabezhinsky for claim 4 above is applied to claim 5.
Regarding claim 6 herein, the claims of ’313 lack “a third buffer” as recited. However, related reference Zabezhinsky teaches a circuit comprising a third buffer having an input coupled to the downstream port and an output coupled to the first upstream port, the third buffer configured to generate a third indication of data, wherein the system bus controller is configured to generate the first upstream transmission responsive to the third indication of data (This is a repetition of parts and Zabezhinsky already teaches wherein the Figure 8, Element 818 indicates that the indicated subframe data may be received associated with each of the corresponding channels and buffered before being input or output amongst the upstream and downstream ports of the channels [Zabezhinsky, 9:1-19]).
Similar rationale/motivation to combine claims of ’313 and Zabezhinsky for claim 4 and 5 above is applied to claim 6.
Regarding claim 7 herein, the claims of ’313 lack the recited “fourth buffer”. However, related reference Zabezhinsky teaches a circuit comprising a fourth buffer having an input coupled to the downstream port and an output coupled to the second upstream port, the fourth buffer configured to generate a fourth indication of data responsive to the second upstream frame, wherein the system bus controller is configured to generate the second upstream transmission responsive to the fourth indication of data (This is a repetition of parts and Zabezhinsky already teaches wherein the Figure 8, Element 818 indicates that the indicated subframe data may be received associated with each of the corresponding channels and buffered before being input or output amongst the upstream and downstream ports of the channels [Zabezhinsky, 9:1-19]).
Similar rationale/motivation to combine claims of ’313 and Zabezhinsky for claim 4 is applied to claim 7.
Regarding claims 8 and 10 herein, claim 3 of ’313 recites “wherein the association between of the selected downstream node and the respective upstream frame of the upstream aggregate frame is indicated by a time of reception by the downstream port of the respective upstream frame” and claim 5 of ‘313 recites “wherein the first downstream node is associated with the first downstream frame by an order of transmission of the first downstream frame within the downstream aggregate frame” overlap claims 8 and 10 herein.
In the alternative, to extent an artisan interprets the claims of ‘313 lack the “association… indicated by a time of reception” as recited in claims 8 and 10 herein. However, related reference Zabezhinsky teaches a circuit comprising “wherein the association… is indicated by a time of reception… respective upstream frame.” For instance, Zabezhinsky teaches a system bus controller (Ser/Des circuitry 212 of Figures 2 and 5-6) having a first downstream port, the system bus controller configured to generate a first downstream frame responsive to the first downstream transmission (the Deserialzers 602 generate a data payload for the wrapped frame 100 as shown in Figure 1 output from the interleaver 608 in response to received data on the input channels (shown in Figures 1, 3 & 6)) [Zabezhinsky, Figures 2, 5 and 6, 7:36-8:67], the system bus controller configured to generate a second downstream frame responsive to the second downstream transmission (Zabezhinsky discloses that this process happens for each of the input channels that is used to receive data and therefore teaches that the generation of a second downstream frame responsive to the second transmission [Zabezhinsky, Figure 6 and also see Figures 1 and 3]), the system bus controller configured to generate a downstream aggregate frame responsive to the first downstream frame and the second downstream frame [Zabezhinsky, Figures 1, 3 and 6, 5:1-60 and 8:1-37 (the first and second data payloads generated from the input data are aggregated into the digital wrapper data frame 100)], the system bus controller configured to transmit the downstream aggregate frame at the first downstream port [Zabezhinsky, Figure 6 (transmitted from interleaver as aggregate frame), 8:25-37 transmitted digital wrapper frames)], the system bus controller adapted to receive an upstream aggregate frame that includes a first upstream frame and a second upstream frame, the system bus controller configured to generate the first upstream transmission responsive to the first upstream frame, and the system bus controller configured to generate the second upstream transmission responsive to the second upstream frame (Fig. 5 depicts the receiving (508 of Figure 5 of Zab), on the system bus (framer 502 side), of an upstream aggregate frame shown as the reception of a digital wrapper data frame (508), then proceeds to generate a first and second upstream frame transmission by reformatting and deinterleaving the incoming data frames (508) into a plurality of subframe structures which are to be forwarded to each of their corresponding different transmit channels) [Zabezhinsky, Figure 5, 7:5-36]. This shows the recited time of reception.
Zabezhinsky is deemed herein to be relevant prior art due to either being in the same field of endeavor or being reasonably pertinent to the particular problem with which the Applicant was faced. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). The level of ordinary skill in the art is shown by the applied art herein. Since claims of ‘313 and Zabezhinsky each regard a circuit, in consideration consistent with US Supreme Court decision in KSR that ‘known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art’, in this case, it would have been obvious to an artisan to add “wherein the association… is indicated by a time of reception… respective upstream frame” and “wherein the first and second indications are based on a time of reception of the first upstream frame and the second upstream frame” as taught by Zabezhinsky to improve the circuit in claims of ’313 with the motivation would have been to increase performance of the communication of multiple devices over a shared link at high speeds.
Regarding claim 11 herein, claim 2 of ‘313 recites “wherein the association between of the selected downstream node and the respective upstream frame of the upstream aggregate frame is indicated by an address included in the upstream aggregate frame” and claim 4 of ‘313 recites “wherein the first downstream node is associated with the first downstream frame by an address of the first downstream node included in the first downstream frame” that overlaps claim 11 herein.
Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 11,736,313 in view of U.S. Pat. No. 7,362,779 (hereinafter Zabezhinsky) as applied to claim 9 above, and further in view of U.S. Pat. App. No. 2018/0060269 (hereinafter Kessler). In the alternative, lacking evidence to the contrary, with broadest reasonable interpretation of the claims without reading limitations from disclosure of ‘804 into the claims herein, although the claims at issue are not identical, they are not patentably distinct from each other for the following reason: while an Applicant/inventor is entitled to one patent for one invention, in comparing Claims 1-8 of U.S. 11736313 to Claims of the instant application, the Claims 1-8 of U.S. 11736313 are an obvious variant that contain substantially the same subject matter that overlaps Circuit herein as discussed above relied on herein and for reasons as further discussed next.
Regarding claim 11 herein, claims of ‘313 in combination with Zabezhinsky lack reciting “wherein the first indication is based on an address of the first downstream node included in the first upstream frame, and the second indication is based on an address of the second downstream node included in the second upstream frame.” However, related reference Kessler describes this element. For instance, related reference Kessler teaches wherein the first downstream node is associated with the first downstream frame by an address (address based on the ID of the Node #2) of the first downstream node (Slave Node 2) included in the first downstream frame [See Kessler, Fig. 11, ¶57 (also the addressing number of the frame and the Slave Node numbering)]. Kessler is deemed herein to be relevant prior art due to either being in the same field of endeavor or being reasonably pertinent to the particular problem with which the Applicant was faced. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). The level of ordinary skill in the art is shown by the applied art herein. Since claims of ‘313, Zabezhinsky and Kessler each regard a circuit, in consideration consistent with US Supreme Court decision in KSR that ‘known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art’, in this case, it would have been obvious to an artisan to add “wherein the first indication is based on an address of the first downstream node included in the first upstream frame, and the second indication is based on an address of the second downstream node included in the second upstream frame” as taught by Kessler to improve the Circuit of claims of ‘313 combined with Zabezhinsky with the resulting benefit would have been the ability to maintain ordering and assignment of the respective data and its corresponding node.
Claims 2-3 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 11,736,313 in view of U.S. Pat. No. 7,362,779 (hereinafter Zabezhinsky) as applied to claim 1 above, and further in view of U.S. Pat. App. No. US 2001/0012692 (hereinafter Miller). Lacking evidence to the contrary, with broadest reasonable interpretation of the claims without reading limitations from disclosure of ‘804 into the claims herein, although the claims at issue are not identical, they are not patentably distinct from each other for the following reason: while an Applicant/inventor is entitled to one patent for one invention, in comparing Claims 1-8 of U.S. 11736313 to Claims of the instant application, the Claims 1-8 of U.S. 11736313 are an obvious variant that contain substantially the same subject matter that overlaps Circuit herein as discussed above relied on herein and for reasons as further discussed next.
Regarding claim 2, the claims of ‘313 lack “a substrate” as recited herein. However, related reference Zabezhinsky teaches a circuit further comprising a substrate, wherein the first local controller, the second local controller, and the system bus controller are arranged on the substrate [Zabezhinsky, Figure 2, 3:57-67 (Zabezhinsky teaches wherein the transmitting and receiving elements in addition to the ser/des may be located on the same card 202 using a common architecture as shown in Figure 2, element 200)], but does not explicitly teach that the first and second local controller are also included on the board/substrate. But, related reference Miller is utilized to teach wherein the discrete parts of a circuit may exist in combination on a common substrate as a hybrid circuit having monolithic semiconductor properties [Miller, ¶3].
Zabezhinsky and Miller is each deemed herein to be relevant prior art due to either being in the same field of endeavor or being reasonably pertinent to the particular problem with which the Applicant was faced. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). The level of ordinary skill in the art is shown by the applied art herein. Since claims of ‘313, Zabezhinsky and Miller each regard a circuit or a circuit on a substrate, in consideration consistent with US Supreme Court decision in KSR that ‘known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art’, in this case, it would have been obvious to an artisan to add “a substrate, wherein the first local controller, the second local controller, and the system bus controller are arranged on the substrate” as taught by Zabezhinsky and Miller to improve the circuit in claims of ’313 with the motivation to enable the circuit devices may be co-located and exist on a single monolithic semiconductor substrate. The resulting benefit would have been the increased performance and board size reduction [Miller, ¶3].
Regarding claim 3, the combination of claims of ’313 in view of Zabezhinsky and Miller teaches that the circuit of claim 2, wherein the substrate is a monolithic semiconductor substrate, and wherein the first local controller, the second local controller, and the system bus controller are formed on the substrate [See the rejection of claim 2.]
The rationale applied to the rejection of claim 2 is hereby applied to reject claim 3].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 4-11 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0010329 (hereinafter Tang), in view of US 7,362,779 (hereinafter Zabezhinsky) and US 2018/0060269 (hereinafter Kessler).
Lacking evidence to the contrary, regarding claim 1,
Tang teaches a circuit [Tang, Fig. 3A], comprising:
a first local controller (device 200-(2)) having a first upstream port (Upper transceiver having a lower interface port "DataU" 202)[Tang, Fig. 3A ¶38] adapted to be coupled to a first local bus (interconnection harnesses 400 which exists as a local Bus connected to the ports of each device 200) and adapted to receive a first local bus transmission via the first local bus [Tang, ¶38-¶40 (data is communicated by each device 200, whereby the interface port "DataU" 202 is the port used by device 200 for receiving a local transmission along the bus 400)], and the first local controller (device 200-(2)) configured to transmit a first upstream transmission via the first upstream port [Tang, ¶38-¶40 (data is communicated by each device 200, whereby the interface port "DataU" 202 is the port used by device 200 for transmitting upstream local transmission along the bus 400)];
a second local controller (200-(N-1)) having a second upstream port (Upper transceiver having a lower interface port "DataU" 202)[Tang, Fig. 3A ¶38] adapted to be coupled to a second local bus (interconnection harnesses 400 which exists as a local Bus connected to the ports of each device 200) and adapted to receive a second local bus transmission via the second local bus [Tang, ¶38-¶40 (data is communicated by each device 200, whereby the interface port "DataU" 202 is the port used by device 200 for receiving a local transmission along the bus 400)], and the second local controller (device 200-(N-1)) configured to transmit a second upstream transmission via the second upstream port [Tang, ¶38-¶40 (data is communicated by each device 200, whereby the interface port "DataU" 202 is the port used by device 200 for transmitting upstream local transmission along the bus 400)]; but it does not explicitly disclose the generation of the aggregate frame, but this feature is known as taught by Zabezhinsky.
However, related reference Zabezhinsky teaches a system bus controller (Ser/Des circuitry 212 of Figures 2 and 5-6) having a downstream port adapted to be coupled to a system bus (See Figures 5-6 wherein the system bus are the communication links connected to the Framer 502 and Interleaver 608), the system bus controller configured to generate a first downstream frame responsive to the first local bus transmission (the Deserialzers 602 generate a data payload for the wrapped frame 100 as shown in Figure 1 output from the interleaver 608 in response to received data on the input channels (shown in Figure 6), interpreted as the claimed first local bus transmission) [Zabezhinsky, Figures 2, 5 and 6, Column 7, Line 36-Column 8, Line 67], the system bus controller configured to generate a second downstream frame responsive to the second local bus transmission (Zabezhinsky discloses that this process happens for each of the input channels that is used to receive data and therefore teaches that the generation of a second downstream frame responsive to the second local bus transmission [Zabezhinsky, Figure 6 and also see Figures 1 and 3]), the system bus controller configured to generate a downstream aggregate frame responsive to the first downstream frame and the second downstream frame [Zabezhinsky, Figures 1, 3 and 6 Column 5, Lines 1-60 and Column 8, Lines 1-37 (the first and second data payloads generated from the input data are aggregated into the digital wrapper data frame 100)], the system bus controller configured to initiate transmission of the downstream aggregate frame at the downstream port [Zabezhinsky, Figures 1, 3 and 6, Column 8, Lines 30-37 (The digital wrapper data frames 100 are transmitted from the interleaver)], the system bus controller adapted to receive an upstream aggregate frame that includes a first upstream frame and a second upstream frame, the system bus controller configured to generate the first upstream transmission responsive to the first upstream frame, and the system bus controller configured to generate the second upstream transmission responsive to the second upstream frame (Fig. 5 depicts the receiving (508 of Figure 5 of Zab), on the system bus (framer 502 side), of an upstream aggregate frame shown as the reception of a digital wrapper data frame (508), then proceeds to generate a first and second upstream frame transmission by reformatting and deinterleaving the incoming data frames (508) into a plurality of subframe structures which are to be forwarded to each of their corresponding different transmit channels) [Zabezhinsky, Figure 5, Column 7, Lines 5-36].
Zabezhinsky is deemed herein to be relevant prior art due to either being in the same field of endeavor or being reasonably pertinent to the particular problem with which the Applicant was faced. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). The level of ordinary skill in the art is shown by the applied art herein. Since Tang and Zabezhinsky each regard a circuit, in consideration consistent with US Supreme Court decision in KSR that ‘known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art’, in this case, it would have been obvious to an artisan to add “receive an upstream aggregate frame that includes a first upstream frame and a second upstream frame, the system bus controller configured to generate the first upstream transmission responsive to the first upstream frame, and the system bus controller configured to generate the second upstream transmission responsive to the second upstream frame” as described by Zabezhinsky to improve the Circuit of Tang to yield the expected result would have been increased performance of the communication of multiple devices over a shared link at high speeds.
To the extent that the combination of Tang with Zabezhinsky does not teach a translator having an input coupled to the downstream port and an output selectively coupled to one of the first upstream port and the second upstream port, the output of the translator selected responsive to an indication of an association between a selected downstream node and a respective upstream frame of the upstream aggregate frame, this feature is known.
However, related reference Kessler teaches further comprising a translator (slave node Figs. 1 & 9/11) having an input coupled to the first upstream port (AN) and the second upstream port (AP of Fig. 1) and an output coupled to the downstream port (BP and link serving as an output of Fig. 1), the translator configured to associate a first downstream node (Slave Node 0) and the first downstream frame (SD 0) and to associate a second downstream node (Slave Node 1) and the second downstream frame (SD 1) [See Kessler, Figs. 10-11, ¶96-¶98 (the association is based on the addressing which corresponds to the position of the frame in the aggregated frame and also the addressing number of the frame and the Slave Node numbering sequence)].
Kessler is deemed herein to be relevant prior art due to either being in the same field of endeavor or being reasonably pertinent to the particular problem with which the Applicant was faced. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). The level of ordinary skill in the art is shown by the applied art herein. Since Tang, Zabezhinsky and Kessler each regard a circuit, in consideration consistent with US Supreme Court decision in KSR that ‘known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art’, in this case, it would have been obvious to an artisan to add “a translator having an input coupled to the downstream port and an output selectively coupled to one of the first upstream port and the second upstream port, the output of the translator selected responsive to an indication of an association between a selected downstream node and a respective upstream frame of the upstream aggregate frame” as described in Kessler to improve the Circuit of Tang with Zabezhinsky to produce the expected resulting benefit would have been the ability to maintain ordering and assignment of the respective data and its corresponding node.
Claim 9 recites similar elements as present in claim 1 herein where the third controller in claim 9 herein is “a system bus controller” in claim 1 where claim 9 similarly recites a first local controller, a second local controller, a system bus controller performing similar/same process recited in claim 1, thus the discussion above regarding claim 1 is relied on for claim 9 herein.
Regarding claim 4, the combination of Tang with Zabezhinsky and Kessler teaches the circuit of claim 1, further comprising a buffer having an input coupled to the first upstream port and an output coupled to the downstream port, the buffer configured to store an indication of data responsive to the first local bus transmission received at a first local bus transmission received at the first upstream port (the Figure 8, Element 818 indicates that the subframe data may be received and buffered before being input or output amongst the upstream and downstream ports of the channels (specifically the first channel) [Zabezhinsky, 9:1-19]), wherein the system bus controller is configured to generate an aggregate frame including a first downstream frame generated responsive to the indication of data wherein the system bus controller is configured to provide the aggregated frame at the downstream port (the indicated received data corresponding to each of the channels when buffered may be generated into a data payload from shown in row 1 of Figure 1 for the downstream frame [Zabezhinsky, 3:14-20 and 4:13-43]). Similar motivation to combine Tang with Zabezhinsky in claim 1 above is applied to claim 4.
Regarding claim 5, the combination of Tang with Zabezhinsky and Kessler teaches the circuit of claim 4, further comprising a circuit wherein the buffer is a first buffer and the indication of data is a first indication of data, and further comprising a second buffer having an input coupled to the second upstream port and an output coupled to the downstream port, the second buffer configured to store a second indication of data responsive to a second local bus transmission (the Figure 8, Element 818 indicates that the subframe data may be received associated with each of the corresponding channels and buffered before being input or output amongst the upstream and downstream ports of the channels [Zabezhinsky, 9:1-19]) received at the second upstream port, wherein the system bus controller is configured to generate a second downstream frame of the aggregate frame, responsive to the second indication of data (the indicated received data corresponding to each of the channels when buffered may be generated into a data payload from shown in row 1 of Figure 1 for the downstream frame [Zabezhinsky, 3:14-20 and 4:13-43]). Similar rationale/motivation to combine Tang with Zabezhinsky for claim 4 above is applied to claim 5.
Regarding claim 6 herein, the combination of Tang with Zabezhinsky and Kessler teaches the circuit of claim 5, further comprising a circuit comprising a third buffer having an input coupled to the downstream port and an output coupled to the first upstream port, the third buffer configured to generate a third indication of data, wherein the system bus controller is configured to generate the first upstream transmission responsive to the third indication of data (This is a repetition of parts and Zabezhinsky already teaches wherein the Figure 8, Element 818 indicates that the indicated subframe data may be received associated with each of the corresponding channels and buffered before being input or output amongst the upstream and downstream ports of the channels [Zabezhinsky, 9:1-19]). Similar rationale/motivation to combine Tang with Zabezhinsky for claim 4 above is applied to claim 6.
Regarding claim 7 herein, the combination of Tang with Zabezhinsky and Kessler teaches the circuit of claim 6, further comprising teaches a circuit comprising a fourth buffer having an input coupled to the downstream port and an output coupled to the second upstream port, the fourth buffer configured to generate a fourth indication of data responsive to the second upstream frame, wherein the system bus controller is configured to generate the second upstream transmission responsive to the fourth indication of data (This is a repetition of parts and Zabezhinsky already teaches wherein the Figure 8, Element 818 indicates that the indicated subframe data may be received associated with each of the corresponding channels and buffered before being input or output amongst the upstream and downstream ports of the channels [Zabezhinsky, 9:1-19]). Similar rationale/motivation to combine Tang with Zabezhinsky for claim 4 is applied to claim 7.
Regarding claims 8 and 10 (these claim recite similar limitation), Tang with Zabezhinsky and Kessler teaches the circuit of claim 6, further comprising a circuit comprising “wherein the association… is indicated by a time of reception… respective upstream frame.” For instance, Zabezhinsky teaches a system bus controller (Ser/Des circuitry 212 of Figures 2 and 5-6) having a first downstream port, the system bus controller configured to generate a first downstream frame responsive to the first downstream transmission (the Deserialzers 602 generate a data payload for the wrapped frame 100 as shown in Figure 1 output from the interleaver 608 in response to received data on the input channels (shown in Figures 1, 3 & 6)) [Zabezhinsky, Figures 2, 5 and 6, 7:36-8:67], the system bus controller configured to generate a second downstream frame responsive to the second downstream transmission (Zabezhinsky discloses that this process happens for each of the input channels that is used to receive data and therefore teaches that the generation of a second downstream frame responsive to the second transmission [Zabezhinsky, Figure 6 and also see Figures 1 and 3]), the system bus controller configured to generate a downstream aggregate frame responsive to the first downstream frame and the second downstream frame [Zabezhinsky, Figures 1, 3 and 6, 5:1-60 and 8:1-37 (the first and second data payloads generated from the input data are aggregated into the digital wrapper data frame 100)], the system bus controller configured to transmit the downstream aggregate frame at the first downstream port [Zabezhinsky, Figure 6 (transmitted from interleaver as aggregate frame), 8:25-37 transmitted digital wrapper frames)], the system bus controller adapted to receive an upstream aggregate frame that includes a first upstream frame and a second upstream frame, the system bus controller configured to generate the first upstream transmission responsive to the first upstream frame, and the system bus controller configured to generate the second upstream transmission responsive to the second upstream frame (Fig. 5 depicts the receiving (508 of Figure 5 of Zab), on the system bus (framer 502 side), of an upstream aggregate frame shown as the reception of a digital wrapper data frame (508), then proceeds to generate a first and second upstream frame transmission by reformatting and deinterleaving the incoming data frames (508) into a plurality of subframe structures which are to be forwarded to each of their corresponding different transmit channels) [Zabezhinsky, Figure 5, 7:5-36]. Similar rationale/motivation to combine Tang with Zabezhinsky for claim 4 is applied to claims 8, 10.
Regarding claim 11 herein, Tang with Zabezhinsky and Kessler teaches the circuit of claim 6, further comprising a circuit comprising “wherein the first indication is based on an address of the first downstream node included in the first upstream frame, and the second indication is based on an address of the second downstream node included in the second upstream frame” where related reference Kessler describes this element. For instance, related reference Kessler teaches wherein the first downstream node is associated with the first downstream frame by an address (address based on the ID of the Node #2) of the first downstream node (Slave Node 2) included in the first downstream frame [See Kessler, Fig. 11, ¶57 (also the addressing number of the frame and the Slave Node numbering)]. Similar rationale/motivation to combine Tang with Zabezhinsky and Kessler for claim 1 is applied to claim 11.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0010329 (hereinafter Tang), in view of US 7,362,779 (hereinafter Zabezhinsky) and US 2018/0060269 (hereinafter Kessler) as applied to claim 1 above, and further in view of U.S. Pat. App. No. US 2001/0012692 (hereinafter Miller). Lacking evidence to the contrary, regarding claim 2, Tang lacks discussing “a substrate” as recited herein. However, related reference Zabezhinsky teaches a circuit of claim 1 further comprising a substrate, wherein the first local controller, the second local controller, and the system bus controller are arranged on the substrate [Zabezhinsky, Figure 2, 3:57-67 (Zabezhinsky teaches wherein the transmitting and receiving elements in addition to the ser/des may be located on the same card 202 using a common architecture as shown in Figure 2, element 200)], but does not explicitly teach that the first and second local controller are included on the board. But, related reference Miller is utilized to teach wherein the discrete parts of a circuit may exist in combination on a common substrate as a hybrid circuit having monolithic semiconductor properties [Miller, ¶3].
Zabezhinsky and Miller is each deemed herein to be relevant prior art due to either being in the same field of endeavor or being reasonably pertinent to the particular problem with which the Applicant was faced. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). The level of ordinary skill in the art is shown by the applied art herein. Since Tang, Zabezhinsky and Miller each regard a circuit or a circuit on a substrate, in consideration consistent with US Supreme Court decision in KSR that ‘known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art’, in this case, it would have been obvious to an artisan to add “a substrate, wherein the first local controller, the second local controller, and the system bus controller are arranged on the substrate” as taught by Zabezhinsky and Miller to improve the circuit in Tang with Zabezhinsky and Kessler with the motivation to enable the circuit devices may be co-located and exist on a single monolithic semiconductor substrate. The resulting benefit would have been the increased performance and board size reduction [Miller, ¶3].
Regarding claim 3, the combination of Tang in view of Zabezhinsky and Kessler and further Miller teaches that the circuit of claim 2, wherein the substrate is a monolithic semiconductor substrate, and wherein the first local controller, the second local controller, and the system bus controller are formed on the substrate [See the rejection of claim 2.]
The rationale applied to the rejection of claim 2 is hereby applied to reject claim 3.
Prior or Concurrent Proceedings
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceed-ing in which the 11,736,313 patent is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation.
Information Material to Patentability
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is mate-rial to patentability of the claims under consideration in this reissue appli-cation. These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Conclusion
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/MARK SAGER/Primary Examiner, Art Unit 3992
Conferees:
/JEFFREY D CARLSON/Primary Examiner, Art Unit 3992
/ALEXANDER J KOSOWSKI/Supervisory Patent Examiner, Art Unit 3992