DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the application filed 11/09/2023 and the preliminary amendment filed 02/27/2024.
Claims 21-40 are presented for examination. Claims 1-20 have been cancelled. Claims 21-40 have been added.
Information Disclosure Statement
2. The Applicants’ Information Disclosure Statement (filed 02/27/2024) has been received, entered into the record, and considered. A copy of PTO 1449 form is attached.
Drawings
3. The drawings filed 11/09/2023 are acceptable for examination purposes.
Specification
4. The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The cross reference related to the application cited in the specification must be updated (i.e., update the relevant status, with PTO serial numbers or patent numbers where appropriate). Correction is required.
Claim Objections
5. Claim 34 is objected to because of the following informalities:
“An system” (line 1) should read “A system”.
Appropriate correction is required.
Double Patenting
6. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 11853784. Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1-19 of U.S. Patent No. 11853784 contain every element of claims 21-40 of the instant application and thus anticipate the claims of the instant application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later application claim is not patently distinct from an earlier claim if the later claim is anticipated by the earlier claim.
Current Application
US Patent No. 11853784
21. an apparatus comprising: circuitry to:
cause a packet received from a para-virtualized virtual machine (VM) to be associated with a virtual function (VF) device of a network interface controller (NIC) based on a 1:1 bonding relationship between the para-virtualized VM and the VF device of the NIC to enable data generated by the para-virtualized VM to be provided to the VF device of the NIC in a zero copy manner; and
cause a packet received through the VF device of the NIC that targets the para-virtualized VM to be associated with the para-virtualized VM based on the 1:1 bonding relationship to enable data for the packet received via the VF device of the NIC to be provided to the para-virtualized VM in a zero copy manner.
1. An apparatus comprising: circuitry to:
generate transmit packet descriptors for packets received from a plurality of para-virtualized virtual machines (VMs) that are separately associated with a respective network interface controller (NIC) virtual function (VF) device from among a plurality of NIC VF devices to enable data for a packet generated by a respective para-virtualized VM to be provided to an associated NIC VF device in a zero copy fashion; and
generate receive packet descriptors for packets received through the plurality of NIC VF devices that are targeting the plurality of para-virtualized VMs to enable data for a packet received via the respective NIC VF device to be provided to the respective para-virtualized VM in a zero copy fashion, wherein the respective para-virtualized VM is associated with the respective NIC VF device based on a device association table.
22. The apparatus of claim 21, wherein the 1:1 bonding relationship is indicated in a device association table.
2. The apparatus of claim 1, wherein the device association table indicates a 1:1 bonding relationship between the respective para-virtualized VM and the respective NIC VF device.
23. The apparatus of claim 21, wherein the circuitry comprises a field programmable gate array or an application-specific integrated circuit.
3. The apparatus of claim 1, wherein the circuitry comprises a field programmable gate array or an application-specific integrated circuit.
24. The apparatus of claim 21, wherein the circuitry is configured to be initialized by a hypervisor.
4. The apparatus of claim 1, wherein the circuitry is configured to be initialized by a hypervisor.
25. The apparatus of claim 21, wherein the circuitry includes an input-output memory map unit (IOMMU) to perform direct memory access (DMA) remapping and interrupt remapping for a guest memory space arranged to maintain the data generated by the para-virtualized VM and for a host memory space arranged to maintain the data for the packet received via the VF device of the NIC.
5. The apparatus of claim 1, wherein the circuitry includes an input-output memory map unit (IOMMU) to perform direct memory access (DMA) remapping and interrupt remapping for a guest memory space arranged to maintain the data for the packet generated by the respective para-virtualized VM and for a host memory space arranged to maintain the data for the packet received via the respective NIC VF device.
26. The apparatus of claim 25, the circuitry further comprising a VF driver to initialize the VF device of the NIC and to provide memory pointers pointing to corresponding receive and transmit packet buffers arranged to utilize the guest memory space to enable the data generated by the para-virtualized VM to be provide to the VF device of the NIC in a zero copy manner and to enable the data for the packet received via the VF device of the NIC to be provided to the para-virtualized VM in a zero copy manner.
6. The apparatus of claim 5, the circuitry further comprising a VF driver to initialize the plurality of NIC VF devices and to fill receive/transmit packet descriptors with memory pointers pointing to corresponding receive and transmit packet buffers maintained in the guest memory space.
27. The apparatus of claim 26, the circuitry further comprising a para-virtualization NIC device backend to interact with the para-virtualized VM for packet input/output (I/O) based on receive and transmit queue pairs included in the receive and transmit packet buffers.
7. The apparatus of claim 6, the circuitry further comprising a para-virtualization NIC device backend to interact with the plurality of para-virtualized VMs for packet input/output (I/O) based on receive and transmit queue pairs residing in the receive and transmit packet buffers maintained in the guest memory space.
28. A method comprising:
causing a packet received from a para-virtualized virtual machine (VM) to be associated with a virtual function (VF) device of a network interface controller (NIC) based on a 1:1 bonding relationship between the para-virtualized VM and the VF device of the NIC to enable data generated by the para-virtualized VM to be provided to the VF device of the NIC in a zero copy manner; and
causing a packet received through the VF device of the NIC that targets the para-virtualized VM to be associated with the para-virtualized VM based on the 1:1 bonding relationship to enable data for the packet received via the VF device of the NIC to be provided to the para-virtualized VM in a zero copy manner.
8. A method comprising:
generating transmit packet descriptors for packets received from a plurality of para-virtualized virtual machines (VMs) that are separately associated with a respective network interface controller (NIC) virtual function VF device from among a plurality of NIC VF devices to enable data for a packet generated by a respective para-virtualized VM to be provided to an associated NIC VF device in a zero copy fashion; and
generating receive packet descriptors for packets received through the plurality of NIC VF devices that are targeting the plurality of para-virtualized VMs to enable data for a packet received via the respective NIC VF device to be provided to the respective para-virtualized VM in a zero copy fashion, wherein the respective para-virtualized VM is associated with the respective NIC VF device based on a device association table.
29. The method of claim 28, wherein the 1:1 bonding relationship is determined based on a device association table.
9. The method of claim 8, wherein the device association table indicates a 1:1 bonding relationship between the respective para-virtualized VM and the respective NIC VF device.
30. The method of claim 28, wherein the method is implemented by circuitry configured to be initialized by a hypervisor.
11. The method of claim 9, comprising initializing, via a hypervisor, the device association table that indicates the 1:1 bonding relationship between the respective para-virtualized VM and the respective NIC VF device.
31. The method of claim 30, wherein the circuitry includes an input-output memory map unit (IOMMU) for: performing direct memory access (DMA) remapping and interrupt remapping of a guest memory space arranged to maintain the data generated by the para-virtualized VM; and performing DMA remapping and interrupt remapping of a host memory space arranged to maintain the data for the packet received via the VF device of the NIC.
12. The method of claim 8, further comprising: performing, using an input-output memory map unit (IOMMU), direct memory access (DMA) remapping and interrupt remapping for a guest memory space arranged to maintain the data for the packet generated by the respective para-virtualized VM and for a host memory space arranged to maintain the data for the packet received via the respective NIC VF device.
32. The method of claim 31, the circuitry further comprising a VF driver for: initializing the VF device of the NIC; and providing memory pointers pointing to corresponding receive and transmit packet buffers arranged to utilize the guest memory space to enable the data generated by the para-virtualized VM to be provide to the VF device of the NIC in a zero copy manner and to enable the data for the packet received via the VF device of the NIC to be provided to the para-virtualized VM in a zero copy manner.
13. The method of claim 12, further comprising: initializing the plurality of NIC VF devices; and filling receive and transmit packet descriptors with memory pointers pointing to corresponding receive and transmit packet buffers maintained in the guest memory space, the initializing and filling being performed by a VF driver.
33. The method of claim 32, the circuitry further comprising a para-virtualization NIC device backend for interacting with the para-virtualized VM for packet input/output (I/O) based on receive and transmit queue pairs included in the receive and transmit packet buffers.
7. The apparatus of claim 6, the circuitry further comprising a para-virtualization NIC device backend to interact with the plurality of para-virtualized VMs for packet input/output (I/O) based on receive and transmit queue pairs residing in the receive and transmit packet buffers maintained in the guest memory space.
34. A system comprising:
a network interface controller (NIC) to include a plurality of virtual function (VF) devices arranged to access a host memory space;
a plurality of para-virtualized virtual machines (VMs) arranged to access a guest memory space; and
circuitry to:
cause a packet received from a para-virtualized VM from among the plurality of para-virtualized VMs to be associated with a virtual function (VF) from among the plurality of VF devices based on a 1:1 bonding relationship between the para-virtualized VM and the VF device of the NIC to enable data generated by the para-virtualized VM to be provided to the VF device of the NIC in a zero copy manner; and
cause a packet received through the VF device of the NIC that targets the para-virtualized VM to be associated with the para-virtualized VM based on the 1:1 bonding relationship to enable data for the packet received via the VF device of the NIC to be provided to the para-virtualized VM in a zero copy manner.
14. A para-virtualization computer system, comprising:
a network interface controller (NIC) to include a plurality of virtual function (VF) devices arranged to access a host memory space;
a plurality of para-virtualized virtual machines (VMs) arranged to access a guest memory space; and
circuitry to:
generate transmit packet descriptors for packets received from the plurality of para-virtualized VMs that are separately associated with a respective VF device from among the plurality of VF devices to enable data for a packet generated by a respective para-virtualized VM to be provided to an associated VF device in a zero copy fashion; and
generate receive packet descriptors for packets received through the plurality of VF devices that are targeting the plurality of para-virtualized VMs to enable data for a packet received via the respective VF device to be provided to the respective para-virtualized VM in a zero copy fashion, wherein the respective para-virtualized VM is associated with the respective VF device based on a device association table.
35. The system of claim 34, wherein the 1:1 bonding relationship is indicated in a device association table.
15. The system of claim 14, wherein the device association table indicates a 1:1 bonding relationship between the respective para-virtualized VM and the respective NIC VF device.
36. The system of claim 34, wherein the circuitry comprises a field programmable gate array or an application-specific integrated circuit.
16. The system of claim 14, wherein the circuitry comprises a field programmable gate array or an application-specific integrated circuit.
37. The system of claim 34, wherein the circuitry is configured to be initialized by a hypervisor.
4. The apparatus of claim 1, wherein the circuitry is configured to be initialized by a hypervisor.
38. The system of claim 34, wherein the circuitry includes an input-output memory map unit (IOMMU) to perform direct memory access (DMA) remapping and interrupt remapping for a guest memory space arranged to maintain the data generated by the para-virtualized VM and for a host memory space arranged to maintain the data for the packet received via the VF device of the NIC.
17. The system of claim 14, wherein the circuitry includes an input-output memory map unit (IOMMU) to perform direct memory access (DMA) remapping and interrupt remapping for the guest memory space, the guest memory space arranged to maintain the data for the packet generated by the respective para-virtualized VM and for a host memory space, the host memory space arranged to maintain the data for the packet received via the respective VF device.
39. The system of claim 38, the circuitry further comprising a VF driver to initialize the VF device of the NIC and to provide memory pointers pointing to corresponding receive and transmit packet buffers arranged to utilize the guest memory space to enable the data generated by the para-virtualized VM to be provide to the VF device of the NIC in a zero copy manner and to enable the data for the packet received via the VF device of the NIC to be provided to the para-virtualized VM in a zero copy manner.
18. The system of claim 14, the circuitry further comprising a VF driver is to initialize the plurality of VF devices and to fill receive and transmit packet descriptors with memory pointers pointing to corresponding receive and transmit packet buffers maintained in the guest memory space.
40. The system of claim 39, the circuitry further comprising a para-virtualization NIC device backend to interact with the para-virtualized VM for packet input/output (I/O) based on receive and transmit queue pairs included in the receive and transmit packet buffers.
19. The system of claim 18, the circuitry further comprising a para-virtualization NIC device backend to interact with the plurality of para-virtualized VMs for packet input/output (I/O) based on receive and transmit queue pairs residing in the corresponding receive and transmit packet buffers maintained in the guest memory space.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C.
102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 21-26, 28-32, and 34-39 are rejected under 35 U.S.C. 103 as being unpatentable over Droux et al. in view of Thakkar (US 20100070677). The references were cited by Applicant in the IDS filed 02/27/2024.
It is noted that any citations to specific, pages, columns, paragraphs, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
As to claim 21:
Droux teaches an apparatus (the computing system; [0045]) comprising: circuitry to:
cause a packet received from a para-virtualized virtual machine (VM) to be associated with a virtual function (VF) device of a network interface controller (NIC) based on a 1:1 bonding relationship between the para-virtualized VM and the VF device of the NIC to enable data generated by the para-virtualized VM to be provided to the VF device of the NIC ([0020-0022]: The packets received by the NI are then forwarded to other components on the physical NIC (102) for processing, etc. Further, in one embodiment of the invention, the physical NIC (102) may include a direct memory access (DMA) engine (not shown), which includes functionality to transfer packets from the NIC to the host (100)… The NIC virtual functions (NIC virtual function A (112A), NIC virtual function B (112B)) may be assigned to elements executing on the computer system (100), such as VNICs (e.g., VNIC (108)) and/or virtual machines (e.g., virtual machine A (106A), virtual machine B (106B)). Assigning a NIC virtual function (NIC virtual function A (112A), NIC virtual function B (112B)) provides the VNIC (108) and/or the virtual machines (e.g., virtual machine A (106A), virtual machine B (106B)) with control of NIC resources allocated to that NIC virtual function (allocated NIC resources A (116A), allocated NIC resources B (116B)). Further, the virtual functions (NIC virtual function A (112A), NIC virtual function B (112B)) enable virtual machines (virtual machine A (106A), virtual machine B (106B)) to transfer data directly from the physical NIC (102) into memory allocated for the virtual machine (i.e., without first copying the data into memory controlled by the host OS (104)); and
cause a packet received through the VF device of the NIC that targets the para-virtualized VM to be associated with the para-virtualized VM based on the 1:1 bonding relationship to enable data for the packet received via the VF device of the NIC to be provided to the para-virtualized VM ([0030-0031]: the host OS sends instructions to the VNIC (108) and shadow VNIC (110) to alter parameters of the allocated NIC resources (allocated NIC resource A (116A), allocated NIC resource B (116B)). Such parameters may include the kind and amount of resources in the allocated NIC resources (allocated NIC resource A (116A), allocated NIC resource B (116B)). Such parameters may also include the way in which data packets sent and received by the virtual machines (virtual machine A (106A), virtual machine B (106B)) are handled. For example, altering certain parameters may cause the VNIC (108) or shadow VNIC (110) to gather metrics about the data packets, filter a subset of data packets, and/or inspect data packets. In one or more embodiments of the invention, the altering the parameters may include changing a MAC address associated with the virtual machine…the shadow VNIC (110) communicates with the NIC physical function (114) via control path B (120B) to service configuration and information requests from the host OS (104). Further, by mapping NIC virtual function B (112B) directly to virtual machine B 106B, Virtual machine B (106B) may utilize the functionality of the NIC virtual function, such as configuring the resources within allocated NIC resources B (116B) and transferring data packets directly between memory in virtual machine B (106B) and memory on the physical NIC (102) via data path C (118C) (i.e., without first coping the data packets to other memory on computer system (100)).
Droux, however, does not explicitly teach, Thakkar teaches the claimed “a zero copy manner” ([0030]: FIG. 7 provides a consolidated view of interactions among the various components discussed in the context of FIGS. 1 through 5 where such interactions circumvent the step of copying data (i.e., step 510 of FIG. 5) from buffer 228 of hypervisor memory 224 to buffer 428 of guest operating system memory 424, i.e., when zero-copy techniques are being employed in accordance with one or more embodiments of the invention. Here, descriptor ring 200 is dedicated to servicing VM 120.sub.1 and thus contains free buffer addresses from guest operating system memory space 424 rather than from hypervisor memory space 224. When NIC 108 receives network data and obtains an address of a buffer from the descriptor pointed to by consumer pointer 208, the address, such as 416, resides in guest operating system memory space 424. As such, incoming network data is written by NIC 108 directly into buffer 428 in memory space 424 of guest operating system 132, as indicated by arrow 700. When ownership of buffer 428, as set in the descriptor in descriptor ring 200, is handed off from NIC 108 to hypervisor 112 (as in step 308), hypervisor 112, via VNIC 128, copies address 416 of buffer 428 into the address entry of the descriptor in descriptor ring 400 pointed to by consumer pointer 408 as indicated by arrow 705. Hypervisor 112 then changes ownership of buffer 428, as set in the descriptor of descriptor ring 400, to guest operating system 132 (as in step 512) which is then able to process the network data written into buffer 428).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Droux with Thakkar because it would have provided the enhanced capability for receiving incoming network data utilizing "zero-copy" techniques.
As to claim 22:
Droux teaches the 1:1 bonding relationship is indicated in a device association table ([0015-0016] and [0021-0023]).
As to claim 23:
Droux teaches the circuitry comprises a field programmable gate array or an application-specific integrated circuit ([0045]).
As to claim 24:
Droux does not explicitly teach, Thakkar teaches the circuitry is configured to be initialized by a hypervisor (hypervisor 112; [0021-0022]).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Droux with Thakkar because it would have provided the enhanced capability for receiving incoming network data utilizing "zero-copy" techniques.
As to claim 25:
Droux teaches the circuitry includes an input-output memory map unit (IOMMU) to perform direct memory access (DMA) remapping and interrupt remapping for a guest memory space arranged to maintain the data generated by the para-virtualized VM and for a host memory space arranged to maintain the data for the packet received via the VF device of the NIC([0003-0004], [0016-0017], and [0020]).
As to claim 26:
Droux teaches a VF driver to initialize the VF device of the NIC and to provide memory pointers pointing to corresponding receive and transmit packet buffers arranged to utilize the guest memory space to enable the data generated by the para-virtualized VM to be provide to the VF device of the NIC and to enable the data for the packet received via the VF device of the NIC to be provided to the para-virtualized VM in ([0031-0034]).
Droux, however, does not explicitly teach, Thakkar teaches the claimed “a zero copy manner” ([0030]: FIG. 7 provides a consolidated view of interactions among the various components discussed in the context of FIGS. 1 through 5 where such interactions circumvent the step of copying data (i.e., step 510 of FIG. 5) from buffer 228 of hypervisor memory 224 to buffer 428 of guest operating system memory 424, i.e., when zero-copy techniques are being employed in accordance with one or more embodiments of the invention. Here, descriptor ring 200 is dedicated to servicing VM 120.sub.1 and thus contains free buffer addresses from guest operating system memory space 424 rather than from hypervisor memory space 224. When NIC 108 receives network data and obtains an address of a buffer from the descriptor pointed to by consumer pointer 208, the address, such as 416, resides in guest operating system memory space 424. As such, incoming network data is written by NIC 108 directly into buffer 428 in memory space 424 of guest operating system 132, as indicated by arrow 700. When ownership of buffer 428, as set in the descriptor in descriptor ring 200, is handed off from NIC 108 to hypervisor 112 (as in step 308), hypervisor 112, via VNIC 128, copies address 416 of buffer 428 into the address entry of the descriptor in descriptor ring 400 pointed to by consumer pointer 408 as indicated by arrow 705. Hypervisor 112 then changes ownership of buffer 428, as set in the descriptor of descriptor ring 400, to guest operating system 132 (as in step 512) which is then able to process the network data written into buffer 428).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Droux with Thakkar because it would have provided the enhanced capability for receiving incoming network data utilizing "zero-copy" techniques.
As to claims 28-32:
Refer to the discussion of claims 21, 22, and 24-26 above, respectively, for rejections. Claims 28-32 are the same as claims 21, 22, and 24-26, except claims 28-32 are method claims and claims 21, 22, and 24-26 are apparatus claims.
As to claim 34:
The rejection of claim 21 above is incorporated herein in full. Additionally, Droux teaches a network interface controller (NIC) to include a plurality of virtual function (VF) devices arranged to access a host memory space (a network interface controller… the NIC virtual function; Abstract, [0003-0005], and [0020-0022]) a plurality of para-virtualized virtual machines (VMs) arranged to access a guest memory space (virtual machines; [0018-0019] and [0022-0024]).
As to claims 35-39:
Refer to the discussion of claims 22-26 above, respectively, for rejections. Claims 35-39 are the same as claims 22-26, except claims 35-39 are system claims and claims 22-26 are apparatus claims.
Allowable Subject Matter
8. Claims 27, 33, and 40 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, subject to the double patenting rejection detailed above, subject to the results of a final search by the Examiner.
Conclusion
9. The prior art made of record, listed on PTO 892 provided to Applicant is considered to have relevancy to the claimed invention. Applicant should review each identified reference carefully before responding to this office action to properly advance the case in light of the prior art.
Contact Information
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VAN H. NGUYEN whose telephone number is (571) 272-3765. The examiner can normally be reached on Monday- Friday from 9:00AM to 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEWIS BULLOCK, can be reached at telephone number (571) 272-3759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VAN H NGUYEN/Primary Examiner, Art Unit 2199
Prosecution Insights