DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/10/23 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
Figure 8 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yohannes (US 2020/0119251).
As to claim 1, Yohannes teaches a quantum device (annotated Fig. 17A-D below) comprising:
a first chip (See fig. below); and
a second chip (see fig. below), the first chip and the second chip assembled to configure a superconducting quantum circuit of a three-dimensional wiring structure ([0132] – [0134]),
wherein the first chip includes:
a protruding region protruded from a side edge of an outer periphery of the second chip ([0132] – [0134]); and
at least one terminal disposed on the protruding region ([0132] – [0134]).
It is noted that figs. 17A-D are different embodiments of the same package.
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As to claim 2, Yohannes further teaches the first chip and the second chip are arranged with a first surface (top) of the first chip opposed to a first surface (bottom) of the second chip, and wherein the superconducting quantum circuit is arranged on at least one of the first surface of the first chip and the first surface of the second chip (fig. 17A).
As to claim 3, Yohannes further teaches the protruding region of the first chip is an outer edge region of the first chip, protruded from the side edge of the outer periphery of the second chip, and wherein the at least one terminal on the outer edge region is provided for testing of at least one of the first chip and the second chip assembled ([0122] testing is done at all or some of the terminals).
As to claim 4, Yohannes further teaches at least one of the first chip and the second chip includes a circuit under test electrically connected to the at least one terminal disposed on the protruding region of the first chip, the circuit under test being tested using the at least one terminal (see rejection of claim 3. At least one part of the chip(s) is being tested, thus it is under test).
As to claim 5, Yohannes teaches the terminals are used to test the entirety of the chips ([0122]). Therefore, the second chip includes a circuit under test on an outer periphery of the second chip (any circuit on the periphery is under test), the circuit under test electrically connected to the at least one terminal disposed on the protruding region of the first chip, the circuit under test being tested using the at least one terminal ([0122]).
As to claim 6, Yohannes teaches the terminals are used to test the entirety of the chips ([0122]). The rejection of claim 5 applies here as well.
As to claim 9, Yohannes further teaches the first chip includes a terminal for external connection on a second surface opposite to a first surface facing the second chip (fig. 17B).
As to claim 10, Yohannes further teaches the second chip includes a terminal for external connection on a second surface opposite to a first surface facing the first chip (fig. 17C).
As to claim 11, Yohannes further teaches the second chip includes a plurality of circuit elements constituting the superconducting quantum circuit within a region on a wiring layer of a first surface of the second chip, the region enclosed by a periphery of the first surface of the second chip (figs. 17A-D, the entire second chip is enclosed by the periphery of the first chip, thus this limitation is met).
As to claims 12-14 and 17, these limitations are directed to bumps on the second chip being connected to pads on the first chip, which are connected via a wiring layer to the terminals on the periphery. This can be seen in fig. 10. Since all of the
As to claim 15, Yohannes further teaches the first surface of the second chip is connected to a second surface of the second chip opposite to the first surface thereof via through vias, the plurality of circuit elements of the superconducting quantum circuit arranged on the first surface of the second chip are connected to a wiring layer on the second surface of the second chip via the though vias, the wiring layer on the second surface of the second chip including a plurality of terminals for external connection (fig. 17D).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yohannes.
As to claim 7, Yohannes does not explicitly teach the circuit under test includes at least one selected from a group including a qubit, a qubit coupler, a resonator, an oscillator, a Superconducting Quantum Interference Device (SQUID), and a magnetic field application circuit. However, Yohannes does teach the second chip is a quantum device (see fig. 17A). Each of these group items are known parts of a quantum device, thus testing them would have been obvious so as to ensure the quantum device works.
Allowable Subject Matter
Claims 8 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art fails to teach a combination of all of the features in the claims. As to claim 8, Yohannes fails to teach the terminals disposed in the protruding region of the first chip includes at least one signal terminal electrically connected to at least one signal line of the circuit under test and at least one ground terminal connected to ground, on both sides of the signal terminal provided the ground terminals disposed, wherein the ground terminal provided between adjacent signal terminals has an area larger than an area of the signal terminal, or at least one ground terminal provided between the adjacent signal terminals, has an area same as an area of the signal terminal.
As to claim 16, Yohannes fails to teach a wiring layer on the first surface of the first chip includes at least a ground plane provided on each longitudinal side of the signal line via a gap, the ground plane extended to a location where the ground terminal is to be disposed to serve as the ground terminal.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any response to this Office Action should be faxed to (571) 273-8300 or mailed to:
Commissioner for Patents
P.O. Box 1450
Alexandria, VA 22313-1450
Hand-Delivered responses should be brought to:
Customer Service Window
Randolph Building
401 Dulany Street
Alexandria, VA 22313
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
7/26/26
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