DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I including claims 1-13 in the reply filed on 03/03/2026 is acknowledged. Claims 14-20 are canceled by Applicants
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over EDELMANN et al (WO 2023051927 A1) in view of Nayak et al (Pat# 7,352,198).
As to claim 1, EDELMANN et al disclose an apparatus as shown in figures 1B-1C comprising: a wafer (100) including integrated circuit dies (101), each integrated circuit die including a plurality of die pads (103), each die pad covered by a protection layer (105) and a probe (107) for perming wafer level testing. According to Edelmann et al, the probe (107) punctures through the protection layer (105) with a distal end of a probe to make physical and electrical contact with the given die pad at a first location at the given die pad and performing a first electrical test of the integrated circuit die through the probe. Eldeman et al do not explicitly mention about horizontally translating after completion of the first electrical test; puncturing through the protection layer with the distal end of the probe to make physical and electrical contact with the given die pad at a second location, different from the first location, at the given die pad; and performing a second first electrical test of the integrated circuit die through the probe.
Nayak et al disclose a probe system as shown in 1 having a stage (114) to move in XYZ direction and a probe card chuck (106) with probe pins (107) for contacting die pad a plurality of locations on a die pad (105) and for performing the test.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have the probe (107) to translate horizontally the probe (107) in the device of Edelmann et al as taught by Nayak et al after completion of the first electrical test and puncturing through the protection layer (105) at different location with the distal end of the probe to make physical and electrical contact with the given die pad (103) at a second location, different from the first location, at the given die pad (107) for the purpose of obtaining accurate test results in order to determine the defects of the die under test.
As to claim 9, EDELMANN et al disclose an apparatus as mentioned in claim 1, wherein, the given die pad (105) has a geometric shape characterized by a line of reflectional symmetry, and wherein horizontally translating comprises moving either the wafer or the probe in a direction parallel to that line of reflectional symmetry.
As to claim 10, in the device of EDELMANN et al in view of Nayak et al, wherein the geometric shape is selected from the group consisting of square and rectangular. Furthermore, it is noted that the shape would not be significant and would not change the operation of the device (see In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)).
As to claim 11, in the device of EDELMANN et al in view of Nayak et al, it appears that each of the first and second locations is located on said line of reflectional symmetry.
As to claim 12, EDELMANN et al in view of Nayak et al disclose an apparatus as mentioned in claim 1 , besides the first and second locations/areas, there are other locations/areas other than first and second locations/areas and the other locations/areas are considered as a reserve area.
As to claim 13, EDELMANN et al in view of Nayak et al disclose an apparatus as mentioned in claim 1. EDELMANN et al in view of Nayak et al do not explicitly mention about determining whether the integrated circuit die is defective based on results of the first and second first electrical tests. However, It would have been obvious that after the first and second first electrical tests , the results of the first and second first electrical test are used to determine the defects of the die.
Allowable Subject Matter
Claims 2-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art does not teach the step of identifying a physical pad of the given die pad; identifying a first logical pad area within the physical pad; positioning the probe at the first location which is inside the first logical pad area; identifying a second logical pad area within the physical pad; positioning the probe at the second location which is inside the second logical pad as recited in claim 2. Claims 3-8 depend from objected claim 2, they are also objected to.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hembree et al (Pat# 7.049,840) disclose Hybrid Interconnect And System For Testing Semiconductor Dice.
Farnworth et al (Pat# 6,285,201) disclose Method And Apparatus For Capacitively Testing A Semiconductor Die.
Wark et al (Pat# 5,929,521) disclose Projected Contact Structure For Bumped Semiconductor Device And Resulting Articles And Assemblies.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINH P NGUYEN whose telephone number is (571)272-1964. The examiner can normally be reached M-F 6:00am-4:00pm.
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/VINH P NGUYEN/Primary Examiner, Art Unit 2858
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