Prosecution Insights
Last updated: April 19, 2026
Application No. 18/388,595

THERMAL DROOP COMPENSATION IN POWER AMPLIFIERS

Non-Final OA §102
Filed
Nov 10, 2023
Examiner
CHOE, HENRY
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qorvo US Inc.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
65%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
1238 granted / 1339 resolved
+24.5% vs TC avg
Minimal -27% lift
Without
With
+-27.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
29 currently pending
Career history
1368
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
37.4%
-2.6% vs TC avg
§102
47.1%
+7.1% vs TC avg
§112
3.8%
-36.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1339 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5, 9 and 11-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Ridgers et al (Fig. 2); 9,548,701]. Regarding claims 1, 11, 12 and 18, Ridgers et al discloses an amplifier circuit comprising a power amplifier (Q1), an active bias circuit (5, 1) coupled to the power amplifier (Q1) and the active bias circuit (5, 1) comprising a heat-sensitive element (Q2, R3), a droop circuit (15) coupled to the heat-sensitive element (Q2, R3), wherein the droop circuit (15) comprising a current mirror (M1, M2) configured to draw current responsive to changes in the heat-sensitive element (Q2, R3) and generate a trigger signal (the signal generating at the drain terminal of M1), and a correction circuit (Q3) coupled to the power amplifier (Q1) and the droop circuit (15) and configured to receive the trigger signal (the signal generating at the drain terminal of M1) and responsive to receipt of the trigger signal and provide a thermal droop correction to the power amplifier (Q1). Regarding claim 2, wherein the heat-sensitive element (Q2, R3) comprises a transistor (Q2). Regarding claims 3 and 13, wherein the transistor (Q2) comprises a heterojunction bipolar transistor. Regarding claims 4, 16 and 17, wherein the correction circuit (Q3) comprises a variable gain amplifier. Regarding claims 5, 14 and 15, wherein the correction circuit (Q3) comprises an attenuator (resistance in Q3). Regarding claim 9, wherein the current mirror (M1, M2) comprises two transistors. Allowable Subject Matter Claims 6-8 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (571)272-1760. The examiner can normally be reached Mon-Fri 6:00 AM- 6:00 PM EST. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interview practice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea J Lindgren Baltzell can be reached on (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /HENRY CHOE/ Primary Examiner, Art Unit 2843 #2949
Read full office action

Prosecution Timeline

Nov 10, 2023
Application Filed
Feb 24, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603612
POWER SUPPLY CONTROL SYSTEM
2y 5m to grant Granted Apr 14, 2026
Patent 12603625
STACKED DIGITAL CURRENT STEERING AUTOMATIC GAIN CONTROL ATTENUATOR
2y 5m to grant Granted Apr 14, 2026
Patent 12597890
OVER TEMPERATURE PROTECTION OF LDO CONTROLLING THE RF POWER AMPLIFIER COLLECTOR VOLTAGE
2y 5m to grant Granted Apr 07, 2026
Patent 12597893
SEMICONDUCTOR INTEGRATED CIRCUIT AND RADIO-FREQUENCY MODULE
2y 5m to grant Granted Apr 07, 2026
Patent 12597888
ADAPTIVE STABILIZATION AND/OR PERFORMANCE OPTIMIZATION OF POWER AMPLIFIERS
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
65%
With Interview (-27.4%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 1339 resolved cases by this examiner. Grant probability derived from career allow rate.

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