Prosecution Insights
Last updated: August 18, 2026
Application No. 18/388,912

DISPLAY DEVICE

Final Rejection §103
Filed
Nov 13, 2023
Priority
Nov 29, 2022 — RE 10-2022-0162842
Examiner
CHIEN, LUCY P
Art Unit
2871
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
3 (Final)
83%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
771 granted / 929 resolved
+15.0% vs TC avg
Moderate +5% lift
Without
With
+5.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
25 currently pending
Career history
942
Total Applications
across all art units

Statute-Specific Performance

§103
56.8%
+16.8% vs TC avg
§102
32.6%
-7.4% vs TC avg
§112
1.4%
-38.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 929 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1,3-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim(s) 1,3-9,11,14-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 11664355) in view of JEONG IL GI (KR 20170080266 A) Regarding Claim 1, Lee discloses (Fig. 1 to Fig. 2b) a support substrate (160); a plurality of link lines (data lines and/or scan lines) disposed on the support substrate (160); a plurality of display modules disposed on or under the support substrate and including a plurality of pixels (111) and a plurality of signal lines (102); and a plurality of connection members (129) disposed between the support substrate (160) and the plurality of display modules and electrically connecting the plurality of link lines and the plurality of signal lines (102). Lee does not disclose a plurality of first flexible films disposed on one side of the support substrate and electrically connected to one side of the plurality of link links, respectively; and a plurality of second flexible films disposed on another side of the support substrate and electrically connected to another side of the plurality of link lines respectively. JEONG IL GI discloses (Drawing 2) a plurality of first flexible films (410,510) disposed on one side of the support substrate and electrically connected to one side of the plurality of link links, respectively; and a plurality of second flexible films disposed on another side of the support substrate and electrically connected to another side of the plurality of link lines respectively (ABSTRACT) It would have been obvious to one of ordinary skill in the art to modify Lee to include JEONG IL GI’s plurality of first flexible films (410,510) disposed on one side of the support substrate and electrically connected to one side of the plurality of link links, respectively; and a plurality of second flexible films disposed on another side of the support substrate and electrically connected to another side of the plurality of link lines respectively (ABSTRACT) motivated by the desire to drive signals to the chip. Regarding Claim 3, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein each of the plurality of link lines (data line/scan lines) is electrically connected to one of the plurality of first flexible films (taught by JEONG IL GI) at one side thereof, and one of the plurality of second flexible films at another side thereof. Regarding Claim 4, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein the plurality of connection members (129) are disposed in an area (disposed in the pixel region 111) where they overlap with outermost pixels (disposed to overlap light emitting devices 130) among the plurality of pixels. Regarding Claim 5, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein the plurality of connection members (129) are regularly arranged on an entire area of the display module. Regarding Claim 6, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein the plurality of connection members (129) are randomly (may be disposed in the pixel region or non-pixel region. Non uniform placement flexibility = random arrangements) arranged on an entire area of the display module. Regarding Claim 7, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein the plurality of display modules are disposed on the support substrate (160), the plurality of link lines (data lines/scan lines) are disposed on the support substrate (160), the plurality of display modules include a plurality of via holes (121), and the plurality of connection members (129) are disposed in the plurality of via holes and are in contact with the plurality of link lines (data lines/scan lines) and the plurality of signal lines (125). Regarding Claim 8, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein the plurality of display modules is disposed under the support substrate (160), the plurality of link lines (163) are disposed under the support substrate (160), the plurality of display modules include step portions (127), and the plurality of connection members (129) are disposed on the step portions to be electrically connected with the plurality of link lines (163), respectively. Regarding Claim 9, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein end portions of the plurality of link lines (163) are disposed on a same plane as an end portion of the support substrate (160) on another side of the support substrate. Regarding Claim 11, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) further comprising a plurality of anti-corrosion patterns (insulating layer) disposed on the support substrate (160) to cover the plurality of link lines (163). Regarding Claim 14, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein all of the plurality of link lines (163) overlap with the plurality of display modules. Regarding Claim 15, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein one portion of the plurality of link lines (163) overlaps with the plurality of display modules, and another portion of the plurality of link lines (163) is exposed by the plurality of display modules, and another portion of the plurality of link lines is covered by an insulating layer. Regarding Claim 16, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein the plurality of connection members (129) are disposed along an outer area of each of the plurality of display modules. Regarding Claim 17, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) a support substrate (160); and a plurality of display modules disposed on or under the support substrate (160), and each of the plurality of display modules comprises: a substrate including transmissive areas; a plurality of planarization layers (120) disposed on the substrate (160); a plurality of light emitting elements (130) disposed on the substrate; and a bank (structure forming pixel units and organizing discrete light emitting devices into pixel groups consistent with banks which define pixel boundaries and exclusion of transmissive areas) disposed on the substrate, wherein the plurality of planarization layers (120) and the bank are disposed in an area excluding the transmissive area, and are not disposed in the transmissive area (“…The light emitting device 130 may further include additional functional layers in addition to the aforementioned layers. For example, the light emitting device 130 may further include a reflective layer for reflection of light, an additional insulating layer for insulation of a specific component, an anti-solder layer for preventing diffusion of solders, and the like…”) (therefore the planarization layer and bank (the light emitting devices 130) are in the reflective regions). Regarding Claim 18, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein each of the plurality of display modules further comprises a plurality of reflective layers (column 9, lines 13-20) in which they overlap the plurality of light emitting elements, wherein the plurality of reflective layers are disposed in an area excluding the transmissive area. Regarding Claim 19, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) further comprising a plurality of link lines (163) connected to the plurality of link lines (163) on the support substrate (160). Regarding Claim 20, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) further comprising a plurality of signal lines (data lines) disposed on a rear surface of the substrate and electrically connected to the plurality of link lines (163). Regarding Claim 21, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein each of the plurality of display modules further comprises, a first electrode (135a) disposed on the plurality of planarization layers (insulating layer); and a second electrode (135b) disposed on the plurality of planarization layers, wherein the first electrode (135a) and the second electrode (135b) electrically connect the plurality of signal lines (data lines) and the plurality of light emitting elements. Regarding Claim 22, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein the first electrode (135a) and the second electrode (135b) are electrically connected to the plurality of light emitting elements through the plurality of via holes disposed in the plurality of planarization layers (125). Regarding Claim 23, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein each of the plurality of display modules further comprises, a plurality of connection members (129) disposed in the plurality of via holes. Regarding Claim 24, In addition to Lee and JEONG IL GI, Lee discloses (Fig. 1 to Fig. 2b) wherein each of the plurality of link lines (163) extends continuously from one side of the support substrate (160) to another side opposite to the one side. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim(s) 10,12, is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 11664355) and of JEONG IL GI (KR 20170080266 A) in view of Namkung (US 10186688) Regarding Claim 10, Lee and JEONG IL GI discloses everything as disclosed above. Lee and JEONG IL GI does not disclose comprising an end protection member covering the end portions of the plurality of link lines and the end portion of the support substrate. Namkung an end protection member covering the end portions of the plurality of link lines and the end portion of the support substrate (“..an anti-reflective layer…may extend to contact an end portion of the passivation layer..so that the first lateral surface contacting the passivation layer is larger than..”) describes edge/terminal protection structures near panel ends.(Column 8, lines 17-27) It would have been obvious to one of ordinary skill in the art to modify Lee and JEONG IL GI to include Namkung’s end protection member covering the end portions of the plurality of link lines and the end portion of the support substrate motivated by the desire to protect against damages. Regarding Claim 12, In addition to Lee, JEONG IL GI and Namking, Lee discloses wherein the plurality of anti-corrosion patterns (insulating layer) are formed of indium tin oxide. Claim(s) 13, is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 11664355) and of JEONG IL GI (KR 20170080266 A) in view of Kodama et al (US 20050099666) Regarding Claim 13, Lee and JEONG IL GI discloses everything as disclosed above. Lee and JEONG IL GI does not disclose a filling member disposed between the support substrate and the plurality of display modules, wherein a refractive index of the filling member is identical to a refractive index of the support substrate. Kodama et al discloses filling member disposed between the support substrate and the plurality of display modules, wherein a refractive index of the filling member is identical to a refractive index of the support substrate.(ABSTRACT) It would have been obvious to one of ordinary skill in the art to modify Lee and JEONG IL GI to include Kodama et al’s filling member disposed between the support substrate and the plurality of display modules, wherein a refractive index of the filling member is identical to a refractive index of the support substrate motivated by the desire to reduce reflection and improve optical performance. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUCY P CHIEN whose telephone number is (571)272-8579. The examiner can normally be reached 9AM-5PM PST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Caley can be reached at 571-272-2286. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LUCY P CHIEN/Primary Examiner, Art Unit 2871
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Prosecution Timeline

Nov 13, 2023
Application Filed
Sep 23, 2025
Non-Final Rejection mailed — §103
Dec 23, 2025
Response Filed
Jan 26, 2026
Non-Final Rejection mailed — §103
Apr 27, 2026
Response Filed
Jun 04, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
83%
Grant Probability
88%
With Interview (+5.3%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 929 resolved cases by this examiner. Grant probability derived from career allowance rate.

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