DETAILED ACTION
This Office Action is in response to the application filed on 14 November 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim(s) 10 and 17 is/are objected to because of the following informalities: claims 10 and 17 appear to contain the typographical error “SRMA” as an abbreviation for “static random access memory” or (SRAM)
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim(s) 1 and 11 recite(s) the limitation "the plurality of through silicon vias of the … region" in fourth clauses of claims 1 and 11 and the fifth clause of claim 11. While the prior limitations recite a plurality of through vias and first and second regions, it is not clear if the prior limitations establish that the first and the second regions comprise respective pluralities of through vias. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-10 and 12-20 directly or indirectly depend from claims 1 and 11 and are rejected under 35 U.S.C. 112(b) as they incorporate the respective rejected subject matter of claims 1 and 11.
Appropriate corrective action is suggested.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 6-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patil et al. (US 2022/0028756 A1; hereinafter Patil), in view of Metras et al. (US 2019/0385995 A1; hereinafter Metras), in view of Dogiamis et al. (US 2022/0399294 A1; hereinafter Dogiamis).
In regards to claim 1, Patil teaches, e.g. in fig. 4A, a semiconductor device comprising:
a package substrate (450) [0031];
a first die (410) [0030] provided on the package substrate and including a hard macro [0030] and a plurality of through silicon vias (420) [0032]; and
a second die (440-1) provided on the first die and electrically connected (by pads (422)) to the plurality of through silicon vias, and
wherein the first die includes a first region (412) [0030], in which the hard macro is not disposed, and a second region (430/432) [0030-0031] including a macro-region (430) [0030] in which the hard macro is disposed.
Patil appears to be silent as to, but does not preclude, the limitations wherein the plurality of through silicon vias of the regions are arranged in a first direction with a first distance therebetween and in a second direction with a second distance therebetween, wherein the second direction crosses the first direction. Metras teaches, e.g. in figs. 2-3, the limitations wherein the plurality of through silicon vias of the regions are arranged in a first direction (W) with a first distance (p) therebetween and in a second direction (H) with a second distance (s) therebetween, wherein the second direction crosses the first direction [0064]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the plurality of vias taught by taught by Patil with the aforementioned limitations taught by Metras such that the vias have specific respective pitches in different directions to have a device design that reduces manufacturing discard rates and consequently manufacturing costs (Metras [0005]).
The combination of Patil and Metras appears to be silent as to, but does not preclude, the limitations wherein the first pitch is greater than the first distance, and wherein the second pitch is less than the second distance. Dogiamis teaches, e.g. in figs. 2, the limitations wherein the first pitch is greater than the first distance, and wherein the second pitch is less than the second distance ([0043]: standoff layers allowing for pitch translation between layers with the same number of TSVs, but different pitches - pitches under (114-2) different than pitches under (114-3)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Patil and Metras with the aforementioned limitations taught by Dogiamis to allow for IC die compatibility for 3DIC (Dogiamis [0001]).
In regards to claim 2, the combination of Patil, Metras, and Dogiamis teaches the limitations discussed above in addressing claim 1. The combination of Patil, Metras, and Dogiamis appears to be silent as to the limitation wherein the first pitch is in a range of about 100 μm to about 200 μm; however Dogiamis teaches the limitations wherein the pitch between vias is a result effective variable that allows for IC die compatibility [0001]. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitation wherein the first pitch is in a range of about 100 μm to about 200 μm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
In regards to claim 3, the combination of Patil, Metras, and Dogiamis teaches the limitations discussed above in addressing claim 2. The combination of Patil, Metras, and Dogiamis appears to be silent as to the limitation wherein the second pitch is in a range of about 1 μm to about 10 μm; however Dogiamis teaches the limitations wherein the pitch between vias is a result effective variable that allows for IC die compatibility [0001]. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitation wherein the second pitch is in a range of about 1 μm to about 10 μm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
In regards to claim 4, the combination of Patil, Metras, and Dogiamis teaches the limitations discussed above in addressing claim 1. Dogiamis further teaches, e.g. in figs. 2, the limitations further comprising:
connection bumps (110) [0026] interposed between the package substrate (114-1) [0021] and the first die (114-2) [0021], wherein
the first pitch (distance between TSVs under (114-2)) is greater than a pitch between the connection bumps (distance between (110)).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Patil and Metras with the aforementioned limitations taught by Dogiamis to allow for IC die compatibility for 3DIC (Dogiamis [0001]).
In regards to claim 6, the combination of Patil, Metras, and Dogiamis teaches the limitations discussed above in addressing claim 1. Metras further teaches, e.g. in figs. 2-3, the limitations wherein the macro-region (202) extends in the second direction (e.g. fig. 3: in both horizontal axes (H/W)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the plurality of vias taught by taught by Patil with the aforementioned limitations taught by Metras such that the vias have specific respective pitches in different directions to have a device design that reduces manufacturing discard rates and consequently manufacturing costs (Metras [0005]).
In regards to claim 7, the combination of Patil, Metras, and Dogiamis teaches the limitations discussed above in addressing claim 6. Metras further teaches, e.g. in figs. 2-3, the limitations wherein the plurality of through silicon vias of the second region are arranged along a first lateral side of the macro-region and a second lateral side that is opposite to the first lateral side (fig. 3: TSVs (110) are arranged along the peripheral sides, evidenced by (p) and (s) of macro regions (202)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the plurality of vias taught by taught by Patil with the aforementioned limitations taught by Metras such that the vias have specific respective pitches in different directions to have a device design that reduces manufacturing discard rates and consequently manufacturing costs (Metras [0005]).
In regards to claim 8, the combination of Patil, Metras, and Dogiamis teaches the limitations discussed above in addressing claim 1. Patil further teaches the limitations wherein the first die includes a central processing unit (CPU), a graphic processing unit (GPU), or a system on chip (SoC) [0026].
In regards to claim 9, the combination of Patil, Metras, and Dogiamis teaches the limitations discussed above in addressing claim 8. Patil further teaches the limitations wherein the second die includes a central processing unit (CPU), a graphic processing unit (GPU), or a system on chip (SoC) [0026].
In regards to claim 10, the combination of Patil, Metras, and Dogiamis teaches the limitations discussed above in addressing claim 1. Metras further teaches the limitations wherein the hard macro includes a static random access memory (SRAM) [0047]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the plurality of vias taught by taught by Patil with the aforementioned limitations taught by Metras such that the vias have specific respective pitches in different directions to have a device design that reduces manufacturing discard rates and consequently manufacturing costs (Metras [0005]).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Patil, Metras, and Dogiamis as applied to claim 4 above, and further in view of Jeng et al. (US 2013/0087920 A1; hereinafter Jeng).
In regards to claim 5, the combination of Patil, Metras, and Dogiamis teaches the limitations discussed above in addressing claim 4. The combination of Patil, Metras, and Dogiamis appears to be silent as to, but does not preclude, the limitations wherein the connection bumps are C4 bump. Jeng teaches the limitations wherein the connection bumps are C4 bump [0017]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Patil, Metras, and Dogiamis with the aforementioned limitations taught by Jeng to use a comment electrical connections for flip-chips and 3DICs (Jeng [0017]).
Claim(s) 11 and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patil, in view of Metras.
In regards to claim 11, Patil teaches, e.g. in fig. 4A, a semiconductor device comprising:
a package substrate (450) [0031];
a first die (410) [0030] provided on the package substrate and including a hard macro [0030] and a plurality of through silicon vias (420) [0032]; and
a second die (440-1) provided on the first die and electrically connected (by pads (442)) to the plurality of through silicon vias, and
wherein the first die includes a first region (412) [0030], in which the hard macro is not disposed, a second region (430/432) [0030-0031] including a macro-region (430) [0030], in which the hard macro is disposed, and through silicon via groups (fig. 4A: e.g. groups of (420) under (440-1/440-2/440-N) respectively) including the plurality of through silicon vias.
Patil appears to be silent as to, but does not preclude, the limitations wherein the plurality of through silicon vias of the regions are arranged in a first direction with a first distance therebetween and in a second direction with a second distance therebetween, wherein the second direction crosses the first direction. Metras teaches, e.g. in figs. 2-3, the limitations wherein the plurality of through silicon vias of the regions are arranged in a first direction (W) with a first distance (p) therebetween and in a second direction (H) with a second distance (s) therebetween, wherein the second direction crosses the first direction [0064]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the plurality of vias taught by taught by Patil with the aforementioned limitations taught by Metras such that the vias have specific respective pitches in different directions to have a device design that reduces manufacturing discard rates and consequently manufacturing costs (Metras [0005]).
In regards to claim 14, the combination of Patil and Metras teaches the limitations discussed above in addressing claim 11. Patil further teaches, e.g. in fig. 4A, the limitations wherein the first plurality of through silicon vias of each of the through silicon via groups are adjacent to each other (e.g. fig. 4A: the group of (420) under (440-1) is adjacent to the group of (420) under (440-2)).
In regards to claim 15, the combination of Patil and Metras teaches the limitations discussed above in addressing claim 11. Patil further teaches the limitations wherein the first die includes a central processing unit (CPU), a graphic processing unit (GPU), or a system on chip (SoC) [0026].
In regards to claim 16, the combination of Patil and Metras teaches the limitations discussed above in addressing claim 15. Patil further teaches the limitations wherein the second die includes a central processing unit (CPU), a graphic processing unit (GPU), or a system on chip (SoC) [0026].
In regards to claim 17, the combination of Patil and Metras teaches the limitations discussed above in addressing claim 11. Metras further teaches the limitations wherein the hard macro includes a static random access memory (SRAM) [0047]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the plurality of vias taught by taught by Patil with the aforementioned limitations taught by Metras such that the vias have specific respective pitches in different directions to have a device design that reduces manufacturing discard rates and consequently manufacturing costs (Metras [0005]).
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Patil and Metras as applied to claim 11 above, and further in view of Dogiamis.
In regards to claim 12, the combination of Patil and Metras teaches the limitations discussed above in addressing claim 11. The combination of Patil and Metras appears to be silent as to, but does not preclude, the limitations of a minimum distance between through silicon vias. Dogiamis teaches the limitations of a minimum distance between through silicon vias [0043]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Patil and Metras with the aforementioned limitations taught by Dogiamis to allow for IC die compatibility for 3DIC (Dogiamis [0001]).
The combination of Patil, Metras, and Dogiamis appears to be silent as to the limitation wherein a minimum distance between the through silicon via groups in the first direction is a third pitch, and wherein the third pitch is in a range of about 150 μm to about 200 μm; however Dogiamis teaches the limitations wherein the pitch between vias is a result effective variable that allows for IC die compatibility [0001]. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitation wherein a minimum distance between the through silicon via groups in the first direction is a third pitch, and wherein the third pitch is in a range of about 150 μm to about 200 μm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
In regards to claim 13, the combination of Patil, Metras, and Dogiamis teaches the limitations discussed above in addressing claim 12. The combination of Patil, Metras, and Dogiamis appears to be silent as to the limitation wherein a minimum distance between the through silicon via groups in the second direction is a fourth pitch, and wherein the fourth pitch is in a range of about 100 μm to about 150 μm; however Dogiamis teaches the limitations wherein the pitch between vias is a result effective variable that allows for IC die compatibility [0001]. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitation wherein a minimum distance between the through silicon via groups in the second direction is a fourth pitch, and wherein the fourth pitch is in a range of about 100 μm to about 150 μm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Patil, in view of Ning (US 2021/0407571 A1; hereinafter Ning).
In regards to claim 18, Patil teaches a semiconductor device comprising:
a package substrate (450) [0031];
a first die (410) [0030] provided on the package substrate and including a substrate (430/432) [0030-0031] and an active layer (412) [0030];
a rear wire layer (422) [0032] provided on the first die; and
a second die (440) [0032-0033] provided on the rear wire layer,
wherein the active layer includes first through silicon via groups (fig. 4A: e.g. groups of (420) under (440-1)), second through silicon via groups (fig. 4A: e.g. groups of (420) under (440-2)), and a macro-region (430) [0030], wherein the first through silicon via groups include through silicon vias configured to supply a power supply voltage to the second die [0033], and wherein a hard macro [0030] is disposed in the macro-region, and
wherein the macro-region is interposed between the first through silicon via groups (e.g. fig 4A: in a plan view).
Patil appears to be silent as to, but does not preclude, the limitations of a ground wire, wherein the ground wires supply a ground voltage to through silicon vias. Ning teaches, e.g. in fig. 1, the limitations of a ground wire, wherein the ground wires supply a ground voltage to through silicon vias ([0080]: grounding terminal sends ground voltage through TSV). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Patil with the aforementioned limitations taught by Ning to have a semiconductor device with optimized performance (Ning [0005]).
In regards to claim 19, the combination of Patil and Ning teaches the limitations discussed above in addressing claim 18. Ning further teaches, e.g. in fig. 1, the limitations wherein at least a portion of the ground wire is vertically overlapped with the macro-region ([0080]: grounding terminal sends ground voltage through TSV). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Patil with the aforementioned limitations taught by Ning to have a semiconductor device with optimized performance (Ning [0005]).
In regards to claim 20, the combination of Patil and Ning teaches the limitations discussed above in addressing claim 18. Ning further teaches, e.g. in fig. 1, the limitations wherein the first through silicon via groups and the second through silicon via groups are alternately disposed ([0080]: grounding terminal sends ground voltage through TSV). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Patil with the aforementioned limitations taught by Ning to have a semiconductor device with optimized performance (Ning [0005]).
Conclusion
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812