DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The objection to the drawing has been withdrawn.
Specification
The objections to the specification have been withdrawn in light of the Applicant’s amendments.
Response to Arguments
Applicant's arguments filed August 24, 2026 have been fully considered but they are not persuasive. On page 11 of Applicant’s remarks, Applicant argues that Tsao fails to disclose the newly added limitations introduced in the amendment. Regarding layers comprising a nonconductive material and a conductive material, Tsao discloses that the device wafers can be “processed to form features, such as circuits, connecting layers, contacts and other applicable structures”, which would thus have conductive and nonconductive features. Furthermore, in hybrid bonding, which Tsao points out can be used to bond the wafers together, both conductive and nonconductive features are bonded together.
Regarding Applicant’s arguments on page 12 of the limitation of “the direct bond at the bonding site comprises the nonconductive material of the first laver directly bonded to the nonconductive material of the second laver at the bonding site without direct conductor-to-conductor bonds between the first semiconductor element and the carrier,” as described in the 112b rejection below, this limitation can be read as only requiring that the bonding site with the nonconductive elements bonded together be without direct conductor-to-conductor bonds. As such, if the bonding site is just taken to be where the nonconductive elements are bonded, Tsao’s method still meets this limitation. See the rejection of claim 112 below for more details.
Regarding Applicant’s arguments on pages 12 and 13 regarding independent claim 119, since it has been amended analogously to claim 112, Tsao teaches most of these limitations as well, with the exception that Tsao does not explicitly recite the use of singulated dies. However, as can be seen below in the rejection of claim 119, this limitation is rendered obvious over Uzoh 212.
Regarding Applicant’s arguments on pages 14 and 15 regarding independent claim 125, since it has been amended in the same way as claim 112, Tsao likewise teaches the limitations here as well. See the rejection of claim 125 below for more details.
Claim Objections
The objections to claims 116, 123, 128, and 130 have been withdrawn in light of the Applicant’s amendments.
Claim 122 is objected to because of the following informalities: Claim 122 recites “the first singulated die element”. For examination this was interpreted as “the first singulated die”, consistent with other edits to the claim elements. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 112-131 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 112 and 125, in the limitation “the direct bond at the bonding site comprises the nonconductive material of the first laver directly bonded to the nonconductive material of the second laver at the bonding site without direct conductor-to-conductor bonds between the first semiconductor element and the carrier” it is unclear whether the part “without direct conductor-to-conductor bonds between the first semiconductor element and the carrier” is intended to be a descriptor for the bonding site, or a separate limitation that applies to the entirety of the semiconductor element and carrier. This makes the scope of the claim indefinite. For examination this limitation was taken to be a descriptor of the bonding site, i.e. only the bonding site in which the nonconductive materials are bonded needs to be without direct conductor-to conductor bonds.
Claims 113-118 and 126-131 are rejected due to their dependency on claims 112 and 125 respectively.
Regarding claim 119, analogously to the claim above, in the limitation “wherein the direct bond at the bonding site comprises the nonconductive material of the first laver directly bonded to the nonconductive material of the second laver without direct conductor-to-conductor bonds between the first singulated die and the wafer” it is unclear whether the part “without direct conductor-to-conductor bonds between the first singulated die and the wafer” is intended to be a descriptor for the bonding site, or a separate limitation that applies to the entirety of the singulated die and wafer. This makes the scope of the claim indefinite. For examination this limitation was taken to be a descriptor of the bonding site, i.e. only the bonding site in which the nonconductive materials are bonded needs to be without direct conductor-to conductor bonds.
Claims 120-124 are rejected due to their dependency on claim 119.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 112-113 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsao et al. (US 20200108592 A1), hereinafter referred to as Tsao.
Regarding claim 112, Tsao discloses a method of repairing a bonded structure, the method comprising: debonding (paragraph 0029, figure 8) from a carrier including a second laver comprising a nonconductive material and a conductive material (paragraph 0026, Tsao discloses that the wafer 502 can be a device wafer with features such as circuits, connecting layers, and contacts, which would comprise nonconductive and conductive materials) a first semiconductor element including a first laver comprising a nonconductive material and a conductive material (paragraph 0027, second wafer 602 can also be a device wafer, and thus would have nonconductive and conductive materials) the first semiconductor element being directly bonded to a bonding site of the carrier (the wafers “may be bonded through direct or indirect bonding techniques”, paragraph 0028); wherein the direct bond at the bonding site comprises the nonconductive material of the first laver directly bonded to the nonconductive material of the second laver at the bonding site without direct conductor-to-conductor bonds between the first semiconductor element and the carrier (paragraph 0028. The wafers can be bonded with oxide bonding or hybrid bonding, which both have a bonding site with two nonconductive materials bonded together. Here “a bonding site” is taken merely to require a part of the element that is bonded, not necessarily the entire surface) cleaning the bonding site of the carrier (paragraph 0030, According to the inspection result, the first wafer 502 and the second wafer 602 may be replaced, cleaned, or re-polished); and bonding a second semiconductor element to the bonding site of the carrier (figure 9, paragraph 0030, “the second wafer 602 is re-bonded to the first wafer 502” Tsao also states that in some embodiments, the second wafer 602 can be replaced before re-bonding, which would make the bonding process be done with another separate wafer).
Regarding claim 113, Tsao discloses all of the limitations of claim 112. Tsao further discloses the bonding comprises directly bonding the second semiconductor element to the bonding site of the carrier (the re-bonding is “similar as described above for FIG. 7”, which can be direct bonding, see paragraph 0028).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 114-117 and 121 are rejected under 35 U.S.C. 103 as being unpatentable over Tsao in view of Tang et al. (US 20170018450 A1), hereinafter referred to as Tang.
In regards to claim 114, Tsao discloses all of the limitations of claim 112.
Tsao does not disclose reducing a dielectric bond energy via a surface modification of the first semiconductor element and the carrier.
Tang discloses delivering a gas jet to the junction between adjacent layers (paragraph 0036). This jet of gas will naturally reduce the moisture on the surfaces of the layers, which in turn reduces the bond energy. Therefore, Tang discloses reducing a dielectric bond energy via a surface modification of the first semiconductor element and the carrier. Tang also teaches that using this gas jet method can enhance the efficiency, simplify the procedure, provide high wafer throughput, reduce stress on workpiece surface, and uniformly distribute stress and therefore reduce or eliminate the risks for device wafer breakage and internal device damage compared to other mechanical debonding methods (Tang paragraph 0009).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Tsao with the fluid jet debonding of Tang in order to enhance efficiency, simplify the procedure, and reduce the risks for device wafer breakage and internal device damage compared to other mechanical debonding methods.
In regards to claim 115, Tsao discloses all of the limitations of claim 112.
Tsao does not disclose that the debonding the first semiconductor element from the carrier comprises delivering a fluid from one or more nozzles to a bonding interface between the first semiconductor element and the carrier.
Tang discloses the debonding the first semiconductor element from the carrier comprises delivering a fluid from one or more nozzles (350 in Tang figure 2 delivers a gas jet) to a bonding interface between the first semiconductor element and the carrier (between elements 201 and 208 in Tang figure 2). Tang also teaches that this method can enhance the efficiency, simplify the procedure, provide high wafer throughput, reduce stress on workpiece surface, and uniformly distribute stress and therefore reduce or eliminate the risks for device wafer breakage and internal device damage compared to other mechanical debonding methods (Tang paragraph 0009).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Tsao with the fluid jet debonding of Tang in order to enhance efficiency, simplify the procedure, and reduce the risks for device wafer breakage and internal device damage compared to other mechanical debonding methods.
In regards to claim 116, Tsao in view of Tang teach all of the limitations of claim 115.
Tang further teaches delivering the fluid comprises delivering the fluid from a vacuum support tool (the tool 300 in Tang figure 2 has support element 310 that is a vacuum chuck [paragraph 0039]) wherein the vacuum support tool further comprises protrusions extending from the vacuum support tool that surround one or more edges of the first semiconductor element (sections 330 and 340 protrude from the tool and surround at least one edge of the first semiconductor element).
Tang teaches that these are placed around the stack so that the nozzles can blow the gas at the junction and debond the layers (0037), with this method of debonding having the same benefits as described above. Furthermore, the vacuum chuck allows the stack to remain stationary during the process of blowing the gas jets (0037).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the protrusions and vacuum support of Tang in order to better facilitate the gas jet blowing process (as disclosed for claim 115).
In regards to claim 117, Tsao in view of Tang teaches all of the limitations of claim 116. Tang further teaches that the one or more nozzles are disposed within the protrusions (nozzle 350 is in protrusion 330). As these are positioned as the protrusions in Tang described for claim 116, it would be obvious to combine these for the same reasons given there.
Claims 118 is rejected under 35 U.S.C. 103 as being unpatentable over Tsao in view of George et al. (US 8919412 B2), hereinafter referred to as "George".
Referring to claim 118, Tsao discloses all of the limitations of claim 112 with a vacuum support tool.
Tsao does not disclose debonding with contacting a temperature adjustment pad.
George discloses the debonding the first semiconductor element from the carrier comprises: contacting a temperature adjustment pad (159 in George figure 24) disposed on a lower surface of a vacuum support tool (top chuck assembly applies a vacuum. Column 12 lines 1-2) to a top surface of the first semiconductor element (column 11, lines 62-65); wherein the temperature adjustment pad applies a thermal shock (column 11 lines 65-67) to the first semiconductor element to weaken the bond between the first semiconductor element and the carrier (thermal slide process causes the adhesive layer between the elements to become soft, weakening the bond between them).
George also teaches that this method protects extremely thinned wafers from fracture, surface damages, and warping (column 2, lines 8-11). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the debonding procedure of Tsao with the method of George in order to better protect the wafers from fractures, surface damages and warping.
Claims 119-120 and 123-124 are rejected under 35 U.S.C. 103 as being unpatentable over Tsao in view of Uzoh et al. (US 10879212 B2), hereinafter referred to as "Uzoh 212".
Regarding claim 119, Tsao discloses a method of repairing a bonded structure, the method comprising: directly bonding (the wafers “may be bonded through direct or indirect bonding techniques”, paragraph 0028) first singulated die including a first laver comprising a nonconductive material and a conductive material (paragraphs 0027 and 0026, Tsao discloses that the wafer 602 can be a device wafer with features such as circuits, connecting layers, and contacts, which would comprise nonconductive and conductive materials) to a wafer including a second laver comprising a nonconductive material and a conductive material (paragraph 0026, wafer 502 can also be a device wafer, with nonconductive and conductive materials) at a bonding site of the wafer to form a bonded structure (figure 7, paragraph 0028) wherein the direct bond at the bonding site comprises the nonconductive material of the first laver directly bonded to the nonconductive material of the second laver without direct conductor-to-conductor bonds between the first singulated die and the wafer (paragraph 0028. The wafers can be bonded with oxide bonding or hybrid bonding, which both have a bonding site with two nonconductive materials bonded together. Here “a bonding site” is taken merely to require a part of the element that is bonded, not necessarily the entire surface); detecting a bonding defect in the bonded structure after bonding the first semiconductor element to the wafer (steps 1208/1210 in figure 12. Paragraph 0036); debonding the first semiconductor element from the bonding site of the wafer (figure 8, paragraph 0029); and bonding a second semiconductor element to the bonding site of the wafer (figure 9, paragraph 0030).
Tsao discloses wafers/ semiconductor elements, but does not explicitly disclose that the semiconductor element is a singulated die.
Uzoh 212 teaches the use of singulated dies in bonding (Uzoh 212 column 1, lines 14-16). Uzoh 212 also teaches that these can be used in stacked three-dimensional arrangements for various microelectronic packaging schemes, which has the benefit of an increased density of devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use singulated dies in the process of Tsao in order to make three-dimensional stacked arrangements for microelectronic packaging schemes in order to increase the density of devices on the chip.
Regarding claim 120, Tsao in view of Uzoh 212 discloses all of the limitations of claim 119. The combined method further discloses that the bonding comprises directly bonding the second singulated die to the bonding site of the wafer (Tsao paragraph 0028 and 0030).
Regarding claim 123, Tsao in view of Uzoh 212 discloses all of the limitations of claim 119. Tsao does not disclose etching the first singulated die and the bonding dielectric layer of the wafer.
Uzoh 212 teaches etching at least one of an edge of the first singulated die (etched portion of 202’ in Uzoh 212 figure 5C. column 11, lines 26-29 & 50-51) and at least a portion of a bonding dielectric layer of the wafer (bonding oxide layer 204 is etched, column 11 line 16) below the etched edge of the first singulated die (Uzoh 212 figure 5C, etched portion of 204 is below etched portion of 202’).
Uzoh 212 teaches that these etching techniques “provide a reduction of the complexity and cost of direct bond processes for high volume manufacturing”, as well as fewer processing steps, higher manufacturing through-put, and improved profit margin (columns 10 & 11, lines 66-67, 1-14). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the etching steps from the bonding of Uzoh 212 in order to reduce complexity and cost while making bonded electronic devices.
Regarding claim 124, Tsao in view of Uzoh 212 discloses all of the limitations of claim 119. The combined method further discloses removing the first singulated die by applying an upward vacuum force to a top surface of the first singulated die (Tsao paragraph 0018, pulling heads 110a/b apply pull forces using a vacuum).
Claim 121 is rejected under 35 U.S.C. 103 as being unpatentable over Tsao in view of Uzoh 212 as applied to claim 119 above, and further in view of Tang.
In regards to claim 121, Tsao in view of Uzoh 212 discloses all of the limitations of claim 119.
Tsao does not disclose reducing a dielectric bond energy via a surface modification of the first singulated die and the wafer.
Tang discloses delivering a gas jet to the junction between adjacent layers (paragraph 0036). This jet of gas will naturally reduce the moisture on the surfaces of the layers, which in turn reduces the bond energy. Therefore, Tang discloses reducing a dielectric bond energy via a surface modification of the first singulated die and the wafer. Tang also teaches that using this gas jet method can enhance the efficiency, simplify the procedure, provide high wafer throughput, reduce stress on workpiece surface, and uniformly distribute stress and therefore reduce or eliminate the risks for device wafer breakage and internal device damage compared to other mechanical debonding methods (Tang paragraph 0009).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Tsao and Uzoh 212 with the fluid jet debonding of Tang in order to enhance efficiency, simplify the procedure, and reduce the risks for device wafer breakage and internal device damage compared to other mechanical debonding methods.
Claims 122 is rejected under 35 U.S.C. 103 as being unpatentable over Tsao in view of Uzoh 212 as applied to claim 119 above, and further in view of Weaver et al. (US 6068727 A), hereinafter referred to as "Weaver".
In regards to claim 122, Tsao in view of Uzoh 212 discloses all of the limitations of claim 119. Tsao does not disclose protrusions that apply a shear force to the singulated die.
Weaver teaches the debonding a first singulated die element (see claim objection above) from the wafer comprises positioning one or more protrusions extending from a vacuum support tool (50a/50b in Weaver figure 8), the one or more protrusions surrounding one or more edges of the first singulated die (they surround the top substrate 14 in Weaver figure 8) and apply a shear force on the first singulated die (side-to-side rotation causes a shear force, column 6, lines 50-54).
Weaver teaches that this method of separating elements protects them from damage compared to wedge-based methods (Weaver column 3, lines 41-47 ), like that disclosed by Tsao. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Weaver with the method of Tsao ad Uzoh 212 in order to better protect the singulated die from damage.
Claims 125-126 and 131 are rejected under 35 U.S.C. 103 as being unpatentable over Tsao in view of Uzoh et al. (US 11037919 B2), hereinafter referred to as "Uzoh".
In regards to claim 125, Tsao discloses a method of repairing a bonded structure, the method comprising: debonding (Tsao figure 8, paragraph 0029) from a carrier including a second laver comprising a nonconductive material and a conductive material (paragraph 0026, Tsao discloses that the wafer 502 can be a device wafer with features such as circuits, connecting layers, and contacts, which would comprise nonconductive and conductive materials) a first semiconductor element configured for hybrid bonding (the first element can be hybrid bonded to the carrier, and thus would be configured for hybrid bonding, see Tsao paragraph 0028) and including a first laver comprising a nonconductive material and a conductive material (paragraph 0027, second wafer 602 can also be a device wafer, and thus would have nonconductive and conductive materials), the first semiconductor element being directly bonded to a bonding site of a carrier (Tsao paragraph 0028), wherein the direct bond at the bonding site comprises the nonconductive material of the first laver directly bonded to the nonconductive material of the second laver without direct conductor-to-conductor bonds between the first semiconductor element and the carrier (paragraph 0028. The wafers can be bonded with hybrid bonding, which has a bonding site with two nonconductive materials bonded together. Here “a bonding site” is taken merely to require a part of the element that is bonded, not necessarily the entire surface); bonding a second semiconductor element to the bonding site of the carrier (Tsao figure 9, paragraph 0030);
Tsao does not disclose annealing the second semiconductor element and the carrier.
Uzoh discloses annealing the second semiconductor element and the carrier (column 16, lines 5-8). Uzoh teaches that annealing causes metal to expand more than dielectric, causing a metal-to-metal bond in the case of a hybrid bond. Uzoh also teaches that annealing improves the bonding energy and thus the strength of the bond (Uzoh column 15, lines 51-54).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the annealing step of Uzoh to the method of Tsao in order to have a stronger final bond between the semiconductor element and carrier.
In regards to claim 126, Tsao in view of Uzoh teaches all of the limitations of claim 125. Tsao further discloses that the bonding comprises directly bonding the second semiconductor element and the carrier the re-bonding is “similar as described above for FIG. 7”, which can be direct bonding, see paragraph 0028).
In regards to claim 131, Tsao in view of Uzoh teaches all of the limitations of claim 125.
Tsao further discloses attaching a vacuum chuck to the carrier (Tsao paragraph 0018, “The wafer chuck 104 can be a component of a chuck assembly used for holding wafers in place with a fixture that utilizes a vacuum chuck”) and a vacuum support tool to the first semiconductor element (Tsao paragraph 0018, pulling heads 110a/b); and removing the first semiconductor element by applying an upward vacuum force to a top surface of the first semiconductor element (Tsao paragraph 0018, pulling heads 110a/b apply pull forces using a vacuum).
Claims 127-128 are rejected under 35 U.S.C. 103 as being unpatentable over Tsao in view of Uzoh as applied to claim 125 above, and further in view of Tang.
In regards to claim 127, Tsao in view of Uzoh teaches all of the limitations of claim 125. Neither Tsao nor Uzoh teach reducing a dielectric bond energy via a surface modification of the first semiconductor element and the carrier.
Tang discloses delivering a gas jet to the junction between adjacent layers (paragraph 0036). This jet of gas will naturally reduce the moisture on the surfaces of the layers, which in turn reduces the bond energy. Therefore, Tang discloses reducing a dielectric bond energy via a surface modification of the first semiconductor element and the carrier. Tang also teaches that using this gas jet method can enhance the efficiency, simplify the procedure, provide high wafer throughput, reduce stress on workpiece surface, and uniformly distribute stress and therefore reduce or eliminate the risks for device wafer breakage and internal device damage compared to other mechanical debonding methods (Tang paragraph 0009).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Tsao with the fluid jet debonding of Tang in order to enhance efficiency, simplify the procedure, and reduce the risks for device wafer breakage and internal device damage compared to other mechanical debonding methods.
In regards to claim 128, Tsao in view of Uzoh teaches all of the limitations of claim 125. Neither Tsao nor Uzoh teaches debonding using fluids from jets.
Tang teaches the debonding the first semiconductor element from the carrier comprises delivering a fluid from one or more nozzles (350 in Tang figure 2 delivers a gas jet) to a bonding interface between the first semiconductor element and the carrier (between elements 201 and 208 in Tang figure 2) to reduce the bond energy (the jet of gas will naturally reduce the moisture on the surfaces of the layers, which in turn reduces the bond energy), wherein delivering the fluid comprises delivering the fluid from a vacuum support tool (the tool 300 in Tang figure 2 has support element 310 that is a vacuum chuck [paragraph 0039]) wherein the vacuum support tool further comprises protrusions extending from the vacuum support tool and surrounding one or more edges of the first semiconductor element (sections 330 and 340 protrude from the tool and surround at least one edge of the first semiconductor element), and wherein the nozzles are disposed within the protrusions (nozzle 350 is in protrusion 330).
Tang also teaches that this method can enhance the efficiency, simplify the procedure, provide high wafer throughput, reduce stress on workpiece surface, and uniformly distribute stress and therefore reduce or eliminate the risks for device wafer breakage and internal device damage compared to other mechanical debonding methods (Tang paragraph 0009).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Tsao with the fluid jet debonding of Tang in order to enhance efficiency, simplify the procedure, and reduce the risks for device wafer breakage and internal device damage compared to other mechanical debonding methods.
Claim 129 is rejected under 35 U.S.C. 103 as being unpatentable over Tsao in view of Uzoh as applied to claim 125 above, and further in view of George.
In regards to claim 129, Tsao in view of Uzoh teaches all of the limitations of claim 125. Neither Tsao nor Uzoh teaches applying a thermal shock to weaken the bonds between the layers.
George discloses the debonding the first semiconductor element from the carrier comprises: contacting a temperature adjustment pad (159 in George figure 24) disposed on a lower surface of a vacuum support tool (top chuck assembly applies a vacuum. Column 12 lines 1-2) in contact with a top surface of the first semiconductor element (column 11, lines 62-65); wherein the temperature adjustment pad applies a thermal shock (column 11 lines 65-67) to the first semiconductor element to weaken the bond between the first semiconductor element and the carrier (thermal slide process causes the adhesive layer between the elements to become soft, weakening the bond between them); and wherein the thermal shock breaks the bond between the first semiconductor element and the carrier (George column 2 lines 3-4; the heat can decompose the adhesive, thus breaking the bonds).
George also teaches that this method protects extremely thinned wafers from fracture, surface damages, and warping (column 2, lines 8-11). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the debonding procedure of Tsao with the method of George in order to better protect the wafers from fractures, surface damages and warping.
Claim 130 is rejected under 35 U.S.C. 103 as being unpatentable over Tsao in view of Uzoh as applied to claim 125 above, and further in view of Uzoh 212.
In regards to claim 130, Tsao in view of Uzoh teaches all of the limitations of claim 125. Neither Tsao nor Uzoh teaches etching the semiconductor element or bonding dielectric layer.
Uzoh 212 teaches etching at least one of an edge of the first semiconductor element (etched portion of 202’ in Uzoh 212 figure 5C. column 11, lines 26-29 & 50-51) and at least a portion of a bonding dielectric layer of the carrier (bonding oxide layer 204 is etched, column 11 line 16) below the etched edge of the first semiconductor element (Uzoh 212 figure 5C, etched portion of 204 is below etched portion of 202’), wherein the etching comprises sloped profile or a straight profile (the etching is a sloped profile, Uzoh 212 figure 5C, column 11, line 28).
Uzoh 212 teaches that these etching techniques “provide a reduction of the complexity and cost of direct bond processes for high volume manufacturing”, as well as fewer processing steps, higher manufacturing through-put, and improved profit margin (columns 10 & 11, lines 66-67, 1-14). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the etching steps from the bonding of Uzoh 212 in order to reduce complexity and cost while making bonded electronic devices.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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