DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election filed 27 May 2026. Claims 1-20 are pending in this application. Claims 11-17 are withdrawn from consideration, and Claims 1-10, 18-20 are examined in this Office Action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the semiconductor device of Invention I in the reply filed on 27May 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-10, 18, 20 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Tsai et. al (US 2025/0089313 A1).
Regarding Claim 1, Tsai discloses (as shown in Figs. 13A-B) A semiconductor device, comprising:
a top transistor; ([0069] In some embodiments, the lower source/drain regions, and the lower gate structure provide an n-type transistor)
a bottom transistor; ([0069] herein the upper nanostructures, the upper source/drain regions, and the upper gate structure provide a p-type transistor)
an isolation box ([0030] isolation material 100) ([0031] middle semiconductor nanostructures 66M … The isolation structures and the middle semiconductor nanostructures 66M may define boundaries of the lower nanostructure-FETs and the upper nanostructure-FETs.)
between the top transistor and the bottom transistor; (See Fig. 13A, showing the isolation material 100 and middle nanostructures 66M between the upper nanostructures 66U and the lower nanostructures 66L)
a first gate dielectric ([0053] Then, gate dielectrics 130), wherein first portions of the first gate dielectric (130) cover a top surface and top-half of sidewalls of the isolation box (100, 66M); (See Fig. 13B, showing the top surface of the top middle semiconductor layer 66M and the sidewalls of the top middle semiconductor layer 66M and isolation material 100 are covered by the gate dielectric 130)
and a second gate dielectric ([0053] Then, gate dielectrics 130), wherein first portions of the second gate dielectric (130) cover a bottom surface and bottom-half of the sidewalls of the isolation box (66M, 130). (See Fig. 13B, showing the bottom surface of the bottom middle semiconductor layer 66M and the sidewalls of the bottom middle semiconductor layer 66M and isolation material 100 are covered by the gate dielectric 130)
Regarding Claim 2, Tsai further discloses (as shown in Figs. 13A-B) wherein: the top transistor is stacked over the bottom transistor; (See Fig. 13A)
and the top transistor and the bottom transistor are nanosheet field-effect transistors (FETs). ([0010] The CFETs include multiple vertically stacked nanostructure-FETs (e.g., nanowire FETs, nanosheet FETs, multi bridge channel (MBC) FETs, nanoribbon FETs, gate-all-around (GAA) FETs, or the like). For example, a CFET may include a lower nanostructure-FET of a first device type (e.g., n-type/p-type) and an upper nanostructure-FET of a second device type (e.g., p-type/n-type) that is opposite the first device type.)
Regarding Claim 3, Tsai further discloses (as shown in Fig. 13B) wherein: second portions of the first gate dielectric (130) encapsulate a first plurality of nanosheets in the top transistor; ([0053] Specifically, the gate dielectrics 78 may be formed on the top surfaces of the fins 62; on the top surfaces, the sidewalls, and the bottom surfaces of the semiconductor nanostructures 66U, 66L; on the exposed lateral surfaces and the sidewalls of the semiconductor nanostructures 66M, on the sidewalls of the isolation material 100)
and second portions of the second gate dielectric (130) encapsulate a second plurality of nanosheets in the bottom transistor. ([0054] gate dielectrics 130 around the lower semiconductor nanostructures 66L)
Regarding Claim 4, Tsai further discloses (as shown in Fig. 13B) wherein the first portions of the first gate dielectric (130) and the first portions of the second gate dielectric (130) form a continuous layer encapsulating the isolation box (66M, 130). (See Fig. 13B, showing the gate dielectrics 130 fully encircle the middle nanostructures 66M and the isolation material 130)
Regarding Claim 5, Tsai further discloses (as shown in Fig. 13B) wherein: the first gate dielectric (130) is made of a first high-k dielectric material; and the second gate dielectric (130) is made of a second high-k dielectric material. ([0053] The gate dielectrics 130 may include a high-dielectric constant (high-k) material having a k-value greater than about 7.0)
Regarding Claim 6, Tsai further discloses (as shown in Fig. 13B) wherein the first high-k dielectric material and the second high-k dielectric material are a same material. ([0053] The gate dielectrics 130 are conformally formed on the exposed surfaces of the recesses (the removed gate stacks 82/84 and the dummy nanostructures 64) including the semiconductor nanostructures 66, the isolation material 100, and the gate spacers 44)
Regarding Claim 9, Tsai further discloses (as shown in Fig. 13B) an n-type work function metal (nWFM) in the bottom transistor; ([0055] For example, the lower gate electrodes 134L may include one or more work function tuning layer(s) formed of material(s) that are suitable for the device type of the lower nanostructure-FETs. In some embodiments, the lower gate electrodes 134L include an n-type work function tuning layer)
and a p-type work function metal (pWFM) in the top transistor. ([0058] For example, the upper gate electrodes 134U may include one or more work function tuning layer(s) formed of material(s) that are suitable for the device type of the upper nanostructure-FETs) ([0069] wherein the upper nanostructures, the upper source/drain regions, and the upper gate structure provide a p-type transistor)
Regarding Claim 10, Tsai further discloses (as shown in Fig. 13B) wherein the nWFM includes Al or Ti. ([0055] n-type work function tuning layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, or the like)
Regarding Claim 18, Tsai discloses (as shown in Figs. 13A-B) A semiconductor device, comprising:
a top transistor; ([0069] In some embodiments, the lower source/drain regions, and the lower gate structure provide an n-type transistor)
a bottom transistor; ([0069] herein the upper nanostructures, the upper source/drain regions, and the upper gate structure provide a p-type transistor)
a first gate dielectric ([0053] Then, gate dielectrics 130), wherein first portions of the first gate dielectric (130) encapsulate a first plurality of nanosheets in the top transistor; ([0053] Specifically, the gate dielectrics 78 may be formed on the top surfaces of the fins 62; on the top surfaces, the sidewalls, and the bottom surfaces of the semiconductor nanostructures 66U, 66L; on the exposed lateral surfaces and the sidewalls of the semiconductor nanostructures 66M, on the sidewalls of the isolation material 100)
and a second gate dielectric ([0053] Then, gate dielectrics 130), wherein first portions of the second gate dielectric (130) encapsulate a second plurality of nanosheets in the bottom transistor. ([0054] gate dielectrics 130 around the lower semiconductor nanostructures 66L)
Regarding Claim 20, Tsai further discloses (as shown in Fig. 13B) an n-type work function metal (nWFM) in the bottom transistor; ([0055] For example, the lower gate electrodes 134L may include one or more work function tuning layer(s) formed of material(s) that are suitable for the device type of the lower nanostructure-FETs. In some embodiments, the lower gate electrodes 134L include an n-type work function tuning layer)
and a p-type work function metal (pWFM) in the top transistor. ([0058] For example, the upper gate electrodes 134U may include one or more work function tuning layer(s) formed of material(s) that are suitable for the device type of the upper nanostructure-FETs) ([0069] wherein the upper nanostructures, the upper source/drain regions, and the upper gate structure provide a p-type transistor)
Alternatively, Claim 1 can be rejected as anticipated under 35 USC 102a(2) by Chen et. al (US 2024/0321640 A1). Claim(s) 1, 5, 7-8 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Chen et. al (US 2024/0321640 A1).
Regarding Claim 1, Chen discloses (as shown in Fig. 1A-B) A semiconductor device ([0016] FIG. 1A is a cross-sectional view of a stacked device structure 10, in portion or entirety, according to various aspects of the present disclosure. FIG. 1B and FIG. 1C are cross-sectional views of stacked device structure 10, in portion or entirety, along line B-B and line C-C, respectively, of FIG. 1A), comprising:
a top transistor ([0017] an upper transistor 20U (one of devices 12U));
a bottom transistor ([0017] a lower transistor 20L (one of devices 12L));
an isolation box ([0018] respective isolation structure 17 (and semiconductor layers 26M, in the depicted embodiment)) between the top transistor (20U) and the bottom transistor (20L); ([0018] Gate stack 90U is separated from gate stack 90L by a respective isolation structure 17 (and semiconductor layers 26M, in the depicted embodiment))
a first gate dielectric ([0018] Gate dielectric 78U), wherein first portions of the first gate dielectric (78U) cover a top surface and top-half of sidewalls of the isolation box (17, 26M); (See Fig. 1B, showing the top surface of the top semiconductor layer 26M and the sidewalls of the top semiconductor layer 26M and isolation structure 17 are covered by the gate dielectric 78U)
and a second gate dielectric ([0018] Gate dielectric 78L), wherein first portions of the second gate dielectric (78L) cover a bottom surface and bottom-half of the sidewalls of the isolation box (17, 26M). (See Fig. 1B, showing the bottom surface of the bottom semiconductor layer 26M and the sidewalls of the bottom semiconductor layer 26M and isolation structure 17 are covered by the gate dielectric 78L)
Regarding Claim 5, Chen further discloses (as shown in Figs. 1A-B) wherein: the first gate dielectric (78U) is made of a first high-k dielectric material; and the second gate dielectric (78L) is made of a second high-k dielectric material. ([0051] For example, gate dielectric 78U of transistor 20U includes interfacial layers 212 and high-k dielectric layers 215U, and gate dielectric 78L of transistor 20L includes interfacial layers 212 and high-k dielectric layers 215L)
Regarding Claim 7, Chen further discloses (as shown in Figs. 1A-B) wherein the first high-k dielectric material and the second high-k dielectric material are different materials. ([0051] Transistors of stacked device structure 10 are thus provided with different gate dielectrics (i.e., gate dielectrics having different compositions) that may adjust their threshold voltages relative to one another.)
Regarding Claim 8, Chen further discloses (as shown in Figs. 1A-B) wherein: the first gate dielectric (78U) is doped with a metal; and the second gate dielectric (78L) is an undoped material.
([0063] Stacked device structure 10 thus provides a CFET having a first GAA transistor (e.g., transistor 20U, such as an n-type transistor) over a second GAA transistor (e.g., transistor 20L, such as a p-type transistor)… For example, the first GAA transistor may include an N-WFM layer (which is or forms a portion of lower gate electrode 250) and a high-k dielectric layer doped with dipole dopant (e.g., high-k dielectric layer 215L), and the second GAA transistor may include a P-WFM layer (which is or forms a portion of upper gate electrode 260) and a high-k dielectric layer that is not doped with (or doped with a smaller concentration of) the dipole dopant (e.g., high-k dielectric layer 215U))
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai as applied to claim 1 above, and further in view of Chen et. al (US 2024/0321640 A1).
Regarding Claim 7, Tsai fails to disclose wherein the first high-k dielectric material (130) and the second high-k dielectric material (130) are different materials.
Chen discloses (as shown in Figs. 1A-B) wherein the first high-k dielectric material and the second high-k dielectric material are different materials. ([0051] Transistors of stacked device structure 10 are thus provided with different gate dielectrics (i.e., gate dielectrics having different compositions) that may adjust their threshold voltages relative to one another.)
Chen teaches that having different gate dielectrics allows the transistors to have different threshold voltages. ([0051] Transistors of stacked device structure 10 are thus provided with different gate dielectrics (i.e., gate dielectrics having different compositions) that may adjust their threshold voltages relative to one another.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Chen with Tsai in order to have different gate dielectrics in order to adjust the threshold voltages of the transistors.
Regarding Claim 8, Chen further discloses (as shown in Figs. 1A-B) wherein: the first gate dielectric (78U) is doped with a metal; and the second gate dielectric (78L) is an undoped material.
([0063] Stacked device structure 10 thus provides a CFET having a first GAA transistor (e.g., transistor 20U, such as an n-type transistor) over a second GAA transistor (e.g., transistor 20L, such as a p-type transistor)… For example, the first GAA transistor may include an N-WFM layer (which is or forms a portion of lower gate electrode 250) and a high-k dielectric layer doped with dipole dopant (e.g., high-k dielectric layer 215L), and the second GAA transistor may include a P-WFM layer (which is or forms a portion of upper gate electrode 260) and a high-k dielectric layer that is not doped with (or doped with a smaller concentration of) the dipole dopant (e.g., high-k dielectric layer 215U))
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai as applied to claim 18 above, and further in view of Chen et. al (US 2024/0321640 A1).
Regarding Claim 19, Tsai fails to disclose wherein: the first gate dielectric is made of a first high-k dielectric material doped with a metal, and the second gate dielectric is made of a second high-k dielectric material.
Chen further discloses (as shown in Figs. 1A-B) wherein: the first gate dielectric (78U) is doped with a metal; and the second gate dielectric (78L) is made of a second high-k dielectric material.
([0063] Stacked device structure 10 thus provides a CFET having a first GAA transistor (e.g., transistor 20U, such as an n-type transistor) over a second GAA transistor (e.g., transistor 20L, such as a p-type transistor)… For example, the first GAA transistor may include an N-WFM layer (which is or forms a portion of lower gate electrode 250) and a high-k dielectric layer doped with dipole dopant (e.g., high-k dielectric layer 215L), and the second GAA transistor may include a P-WFM layer (which is or forms a portion of upper gate electrode 260) and a high-k dielectric layer that is not doped with (or doped with a smaller concentration of) the dipole dopant (e.g., high-k dielectric layer 215U))
Chen teaches that having different gate dielectrics allows the transistors to have different threshold voltages. ([0051] Transistors of stacked device structure 10 are thus provided with different gate dielectrics (i.e., gate dielectrics having different compositions) that may adjust their threshold voltages relative to one another.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Chen with Tsai in order to have different gate dielectrics in order to adjust the threshold voltages of the transistors.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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