DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the election filed April 8, 2026.
Election/Restrictions
Applicant’s election without traverse of claims 12-18 in the reply filed on April 8, 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The abstract of the disclosure is objected to because the abstract is in method form. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SLIT STRUCTURES IN THREE-DIMENSIONAL SEMICONDUCTIVE DEVICES.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roh et al. (CN 113629060 A) in view of Ishino (US 2020/0273878 A1).
In regard to claim 12, Roh et al. teach a semiconductor device, comprising: an array region (at R1) comprising a first slit structure SL1 extending along a first direction I; and a connection region (at R2) adjacent to the array region (at R1) along a second direction II perpendicular to the first direction I, wherein the connection region (at R2) comprises a second slit structure SL2 extending along the first direction through an insulating layer 74 that extends along the second direction II, and wherein the insulating layer 74 comprises an insulating material (Figures 12A-12B and 16A-16C, pages 21-23).
However, Roh et al. fail to teach ions distributed among the insulating material in the insulating layer.
Ishino teaches ions distributed among the insulating material (of 22) in the insulating layer 22 (Figures 7-8, pages 2-3, paragraphs [0032]-[0036] and [0042], claim 11).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device structure as taught by Roh et al. with the semiconductor device having ions distributed among the insulating material in the insulating layer as taught by Ishino to prevent dielectric breakdown (page 1, paragraph [0003]).
In regard to claim 13, Roh et al. teach a stack of conductive layers 77 and isolating layers 72 alternating with each other along the first direction, wherein each of the first slit structure SL1 and the second slit structure SL2 extends through the stack of conductive layers 77 and isolating layers 72, and wherein the insulating layer 74 is closer to an end of the second slit structure SL2 than the stack of conductive layers 77 and isolating layers 72 along the first direction I (Figures 12A-12B and 16A-16C, pages 21-23).
In regard to claim 14, Roh et al. teach the connection region (at R2) comprising a plurality of contact structures (See Figure 16A at 71(ST)) extending through the stack of conductive layers 77 and isolating layers 72, and wherein at least one of the conductive layers 77 is coupled to a corresponding contact structure (See of Figure 16B at 73C) the plurality of contact structures (See Figure 16 at 71(ST)) (Figures 12A-12B and 16A-16C, pages 21-23).
In regard to claim 15, Roh et al. teach the connection region (at R2) comprising first and second opposite ends (left to right) along the first direction I, and wherein each of the plurality of contact structures (See Figure 16A at 71(ST)) is coupled out to a conductive contact (at 71(ST)) at the first end or the second end (left to right) (Figures 12A-12B and 16A-16C, pages 21-23).
In regard to claim 16, Roh et al. teach the array region (at R1) comprising a plurality of channel structures 34 extending through the stack of conductive layers 77 and isolating layers 72 (Figures 5A, 12A-12B and 16A-16C, pages 14-16 and 21-23).
In regard to claim 17, Roh et al. teach the first slit structure SL1 connecting the second slit structure SL2 along the second direction II, and wherein, along a third direction III perpendicular to the first direction I and the second direction II, a width of the first slit structure SL1 is smaller than a width of the second slit structure SL2 (See Figure 11A) (Figures 11A, 12A-12B and 16A-16C, pages 20-23).
In regard to claim 18, Roh et al. teach the insulating layer 74 comprising a first surface and a second surface along the first direction I, the first surface being closer to the end of the second slit structure SL2 along the first direction I than the second surface (Figures 12A-12B and 16A-16C, pages 21-23). In regard to a first concentration of the ions adjacent to the first surface being higher than a second concentration of the ions adjacent to the second surface of the insulating layer, it is well known in the art of semiconductor devices that the surface facing the ion source has the highest concentration of ions when implanted in an insulating layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The following patents are cited to further show the state of the art with respect to semiconductor devices:
Huo e al. (US 2020/0395374 A1) Koh et al. (CN 114256269 A)
Wu et al. (CN 112992916 A) Xu et al. (CN 112117272 A).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDA M SOWARD whose telephone number is (571)272-1845. The examiner can normally be reached Monday through Thursday, 7am to 5:30pm.
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IMS
April 21, 2026
/IDA M SOWARD/Primary Examiner, Art Unit 2898
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