CTNF 18/389,719 CTNF 81310 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement filed on 11/23/10 has been considered and placed in the application file. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (U.S. 8,779,859) . Regarding claim 1, Su et al. (hereinafter, Ref~859 ) discloses (please see Fig. 5 and related text for details) an amplification circuit (500 of Fig. 5), comprising: an amplifier (305 of Fig. 5) configured to receive an operation current (passing from VDD to GND), and comprising a first terminal (gate of 320 of Fig. 5) configured to receive an input signal (RF_IN of Fig. 5), and a second terminal (drain of 310.2 of Fig. 5) configured to output an amplified input signal (Vout of Fig. 5); a first mirror-branch circuit (420R of Fig. 5) coupled to the amplifier; a second mirror-branch circuit (310.1R or 310.2 of Fig. 5) coupled to the amplifier; a first variable current source (Iref of Fig. 5 can be read as the claimed current source OR at least it is functionally equivalent to it, since VDD_bias may have different voltage levels as described in col. 6, between lines 10-25, thus the current Iref would capable of providing different values) coupled to the first mirror-branch circuit, and configured to generate a first reference current (Iref of Fig. 5); a second variable current source (320R of Fig. 5 can be read as the claimed current source OR at least it is functionally equivalent to it, since the current value would depending on adjustable features connected to gate and or drain of 320R of Fig. 5, for instance, 430.1L of Fig. 5 and/or 430.2L of Fig. 5 and/or RB/CG3 of Fig. 5) coupled to the second mirror-branch circuit, and configured to generate a second reference current (passing through 320R of Fig. 5); and an operational amplifier (OA1 of Fig. 5) comprising a first input terminal (non-inverting terminal of OA1 of Fig. 5) coupled to the second mirror-branch circuit, a second input terminal (inverting input terminal of AO1 of Fig. 5) coupled to the first mirror-branch circuit, and an output terminal (output terminal of OA1 of Fig. 5) coupled to the amplifier; wherein the amplification circuit has a plurality of gain modes (provided by adjustable features including 430.1L and/or 430.2L of Fig. 5), the first reference current is related to the operation current, and the second reference current is related to the operation current, meeting claim 1 . Regarding claim 2, Ref~859 discloses the amplification circuit of claim 1, wherein the first reference current is positively related to the operation current, and the second reference current is positively related to the operation current, since said currents configured in the same manner compared to the claimed one, meeting claim 2 . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 5-20 are allowed. The following is an examiner’s statement of reasons for allowance: Claims 5-20 are allowed over the prior art of record. The prior art of record, considered individually or in combination, fails to fairly teach or suggest the claimed circuit comprising, among other limitations and unobvious limitations of “ a control circuit coupled to the first variable current source and the second variable current source ” structurally and functionally interconnected with other limitations in the manner as cited in the claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /HIEU P NGUYEN/Primary Examiner, Art Unit 2843 Application/Control Number: 18/389,719 Page 2 Art Unit: 2843 Application/Control Number: 18/389,719 Page 3 Art Unit: 2843 Application/Control Number: 18/389,719 Page 4 Art Unit: 2843