DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I and Species Embodiment 1, with corresponding claims 1-14, 16, and 18-25, in the reply filed on 06/05/2026 is acknowledged. Claims 15, 17, and 26-32 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected invention and species embodiments.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE COMPRISING FIRST LIFETIME CONTROL REGION IN TRANSISTOR PORTION AND SECOND LIFETIME CONTROL REGION IN DIODE PORTION.
Claim Objections
Claims 11 and 20-21 are objected to because of the following informalities:
Regarding claim 11, “1.5 X or more” should be changed to “1.5X or more”.
Regarding claim 20, “a ratio I of an active area of the transistor portion to the area of the active portion” should be changed to “the ratio I of the active area of the transistor portion to the area of the active portion of the semiconductor device”.
Regarding claim 21, “the area of the active portion” should be changed to “the area of the active portion of the semiconductor device”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11-14, 16, and 18-25 are rejected under 35 U.S.C. 103 as being unpatentable over Naito (US 2020/0058803 A1).
Regarding claim 1, Naito teaches a semiconductor device (a semiconductor device 100) which includes a transistor portion (a transistor portion 70) and a diode portion (a diode portion 81) (Fig. 3a and paragraphs 45 and 127), comprising:
a drift region of a first conductivity type (an n-type drift region 18) which is provided in a semiconductor substrate (a semiconductor substrate 10) (Fig. 3a and paragraph 84); a plurality of trench portions (dummy trench portions 30 and/or gate trench portions 40) which are provided on a front surface of the semiconductor substrate (an upper surface 21 of 10) (Fig. 3a and paragraphs 81 and 97-99); a buffer region of the first conductivity type (an n-type buffer region 20) which is provided on a side of a back surface of the semiconductor substrate (a lower surface 23 of 10) with respect to the drift region (Fig. 3a and paragraphs 82-85);
a first lifetime control region (a first lower surface side lifetime control region 74) which is provided in the transistor portion (Fig. 3a and paragraphs 100-108); and a second lifetime control region (a second lower surface side lifetime control region 75-1) which is provided at a depth different from that of the first lifetime control region in the diode portion (Fig. 3a and paragraphs 127-128),
wherein when a distance of the first lifetime control region from the back surface in a depth direction is defined as X (μm) (Figs. 3a-3b, a distance of 74 from 23 in μm), a distance of the second lifetime control region from the back surface in the depth direction is defined as Y (μm) (Figs. 3a-3b, a distance of 75-1 from 23 in μm), and a dose amount for forming the second lifetime control region is defined as D (atoms/cm2) (Fig. 3b and paragraphs 140-143, a lifetime killer concentration of 75-1 having helium ions per cm2 implanted in 10),
the distance X and the distance Y satisfy (Mathematical Formula 1) and (Mathematical Formula 2) (Mathematical Formula 1) Y > X (Figs. 3a-3b and paragraph 128 disclosing ““The second lower surface side lifetime control region 75-1 is provided at a deeper position than the first lower surface side lifetime control region 74 with respect to the lower surface 23”); and a ratio I of an active area of the transistor portion to an area of an active portion of the semiconductor device (Fig. 8 and paragraph 200-202, a ratio I of an area of the transistor portion 70 to an area of an active portion 120 of the semiconductor device 100).
While Naito teaches the semiconductor device structurally and compositionally identical to that of claim 1 including (Mathematical formula 1) as discussed above, Naito does not teach “(Mathematical Formula 2) Y ≤ BX – 27B + 1.18 x 10-23D2 – 7.02 x10-11D + 56.89” and “(Mathematical Formula 3) (Mathematical Formula 3) B = -0.139e3.90I”. However, Naito teaches 1) the ratio I of the active area of the transistor portion to the area of the active portion of the semiconductor device (Fig. 8 and paragraph 200-202, the ratio I of the area of the transistor portion 70 to the area of the active portion 120 of the semiconductor device 100), 2) the doping concentration D of the second lower surface side lifetime control region 75-1 (Fig. 3b and paragraphs 140-143, a lifetime killer concentration of 75-1 having helium ions per cm2 implanted in 10), 3) positions of the first lower surface side lifetime control region 74 and the second lower surface side lifetime control region 75-1 from the lower surface 23 of the semiconductor substrate 10 identical to that of (Mathematical Formula 1), and 4) adjusting the lifetime of the carrier by adjusting the depth of the first lower surface side lifetime control region 74 from the lower surface 23 of the semiconductor substrate 10 such that, for example, the tradeoff between the ON voltage and the turn off power loss of the transistor portion 70 can be improved (Figs. 3a-3b and paragraph 108). Then, it would have been obvious to one of ordinary skill in the art to adjust and optimize the distances/depths of the first lower surface side lifetime control region 74 (corresponding to “the first lifetime control region”) and/or the second lower surface side lifetime control region 75-1 (corresponding to “the first lifetime control region”) from the lower surface 23 of the semiconductor substrate 10 with respect (Mathematical formula 2) and (Mathematical formula 2) given the ratio I and the doping concentration D as discussed above in addition to (Mathematical formula 1) to for adjusting and optimizing the lifetime of the carrier as a result-effective variable (i.e., a variable which achieves a recognized result).
Regarding claim 2, Naito teaches wherein the first lifetime control region and the second lifetime control region do not overlap with each other in a top view (Fig. 3a, opposite side portions of 74 and 75-1 do not overlap with each other in a top view).
Regarding claim 3, Naito teaches wherein the first lifetime control region has an overlapping region overlapping with the second lifetime control region in a top view (Fig. 3a, 74 and 75-1 have an overlapping region in a boundary region 90 in a top view).
Regarding claim 4, Naito teaches wherein when a full width at half maximum of a peak of a lifetime killer concentration of the first lifetime control region is defined as W1 (w2 of 74) (Fig. 3b and paragraph 117 and 140). For the formula/equation “Y > X + W1 is satisfied”, the similar reasoning of claim 1 as discussed above is also applied for rejecting claim 4.
Regarding claim 5, Naito teaches wherein when a full width at half maximum of a lifetime killer concentration of a peak for forming the buffer region is defined as Wh (paragraph 120 disclosing “The peak concentration position 76-2 in the first lower surface side lifetime control region 74…may be inside the buffer region 20”). For the formula/equation “Y > X + Wh is satisfied”, the similar reasoning of claim 1 as discussed above is also applied for rejecting claim 5. Furthermore, while Naito does not teach hydrogen as the lifetime killer, it would have been obvious to one of ordinary skill in the art to also utilize hydrogen instead of helium as the lifetime killer element/ion for obtaining the similar function within the semiconductor substrate 10 formed of, for example, silicon.
Regarding claims 6-7, Naito teaches wherein the distance X and the distance Y satisfy Y > 2X (for claim 6) and wherein Y/X, which is a ratio of the distance Y to the distance X, is 1.5 or more and 20 or less (for claim 7) (the similar reasoning of claim 1 as the optimization as discussed above is also applied for rejecting claims 6-7).
Regarding claim 8, Naito teaches comprising a collector region of a second conductivity type (a p-type collector region 22) which is provided on the back surface of the semiconductor substrate (Fig. 3a and paragraph 88), wherein the distance X is larger than a distance in the depth direction between a peak of a doping concentration of the collector region and the back surface (Fig. 3b, 74 is positioned deeper into 18 in 10), and is ¼ or less of a thickness of the semiconductor substrate (paragraph 102, 74 provided in a range ¼ of a thickness T of 10).
Regarding claim 9, Naito teaches wherein the first lifetime control region is provided in the buffer region (paragraph 120).
Regarding claim 11, Naito teaches wherein the distance Y is 1.5 X or more and ½ or less of a thickness of the semiconductor substrate (Figs. 3a-3b and paragraph 122, with 72 provided at a depth T/2 of the substrate and 75-1 is located below 72, the distance Y is ½ or less of a thickness of the semiconductor substrate is satisfied).
Regarding claim 12, Naito teaches wherein the second lifetime control region is provided in the buffer region (paragraph 144 disclosing “The positions 76-2, 76-3 of the peak concentration in the first lower surface side lifetime control region 74 and the second lower surface side lifetime control region 75-1…may be inside the buffer region 20”).
Regarding claim 13, Naito teaches wherein the second lifetime control region is provided on a side of the front surface with respect to the buffer region in the depth direction of the semiconductor substrate (Fig. 3a).
Regarding claim 14, Naito teaches comprising a front-surface-side lifetime control region (an upper surface side lifetime control regions 72) which is provided on a side of the front surface with respect to a center of the semiconductor substrate in the depth direction of the semiconductor substrate is included in the diode portion, and the front-surface-side lifetime control region is provided to extend from the diode portion to the transistor portion in a trench array direction (a y-direction) (Fig. 3a and paragraphs 74-80).
Regarding claim 16, Naito teaches comprising an emitter region of the first conductivity type (an n-type emitter region 12) which is provided on a side of the front surface of the semiconductor substrate with respect to the drift region and has a doping concentration (12 having N+) higher than that of the drift region (18 having N-), wherein the second lifetime control region is provided to extend from the diode portion to the transistor portion in a trench array direction (Fig. 3a and paragraphs 60-61).
Regarding claim 18, Naito teaches wherein the transistor portion has a boundary region (a boundary region 90) provided adjacent to the diode portion (Fig. 3a and paragraph 45), the emitter region is not provided on the front surface of the boundary region (Fig. 3a, the emitter region 12 in 70 is considered as “the emitter region”, which is not provided in 90), and the second lifetime control region is provided to extend from the diode portion to the boundary region in the trench array direction (Fig. 3a).
Regarding claim 19, Naito teaches wherein the second lifetime control region has an extension region extending from a boundary between the transistor portion and the diode portion to an inside of the transistor portion (Fig. 3a). While Naito does not teach that “an area of the extension region in a top view is 10% or less of an area of the second lifetime control region in the top view”, adjusting the width of the extension region of the second lifetime control region (75-1) involves a routine experimentation to obtain the desired extension length, including the claimed percentage, as a design choice of the second lifetime control region.
Regarding claims 20-21, while Naito does not explicitly teach a numerical value for the ratio I (for claim 20) and a numerical value for the area of the active portion 120 (for claim 21), it would have been obvious to one of ordinary skill in the art to determine that the ratio of the transistor portion 70 to the active portion 120 as shown in Naito’s Fig. 8 is substantially within the range of 0.1 or more and 0.9 or less (Fig. 8 and paragraphs 200-202; for claim 20) and the area of the action portion 120 would be readily in a desired dimension in order to provide the desired functionality of the semiconductor device.
Regarding claim 22, Naito teaches wherein the distance X is larger than 0 μm and smaller than a distance from the front surface of the semiconductor substrate to the back surface of the semiconductor substrate (Figs. 3a-3b).
Regarding claim 23, Naito teaches wherein the distance Y is smaller than a distance from the front surface of the semiconductor substrate to the back surface of the semiconductor substrate (Figs. 3a-3b).
Regarding claim 24, Naito teaches wherein the first lifetime control region is provided on the side of the back surface with respect to a center of the semiconductor substrate in the depth direction of the semiconductor substrate (Figs. 3a-3b).
Regarding claim 25, Naito teaches wherein the second lifetime control region is provided on the side of the back surface with respect to a center of the semiconductor substrate in the depth direction of the semiconductor substrate (Figs. 3a-3b).
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kubouchi (US 2020/0357903 A1, Figs. 6A-6B) also teaches a semiconductor device similar to claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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