DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Applicant has submitted a duplicate IDS and will not be considered; the most recent IDS copy of the duplicates will be entered and considered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, 8, 11, 12, 16, 18, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Sanghvi et al. Pub. No. US 2018/0189105 A1 (hereafter Sanghvi), in view of GUTIERREZ et al. Pub. No. US 2020/0089528 A1 (hereafter Gutierrez).
7. Regarding claim 1, Sanghvi teaches “A method, comprising: monitoring, at a hardware signal monitor (HSM) designated memory ... corresponding to at least one first signal received from a first processing unit and at least one second signal received from at least one second processing unit ([0078] teaches a hardware thread scheduler monitoring task schedulers connected to nodes for tasks that reach the end of processing state, wherein it signals the end of task processing for respective schedulers); receiving, at the HSM, a first stored value in the at least one first signal ([0030] teaches a task scheduler sending a pend signal via producer socket to consumer socket wherein [0033] teaches a scheduler crossbar including multiplexers for the signals; [0033] teaches a plurality of signal types such that each type of signal may contain a different value);
receiving, at the HSM, a second stored value in the at least one second signal from at least one second processing unit ([0033] teaches a plurality of task schedulers connected to nodes wherein each task scheduler may produce its own signal);
and notifying, by the HSM, another processing unit in response to processing the at least one first signal based on the first stored value and the at least one second signal based on the second stored value ([0044] teaches a tdone signal indicating that task execution is complete, wherein [0045-0049] teaches that a pend signal may be sent to other task schedulers to indicate that data is available; [0048-0049] says that a task produces a block of data, wherein block of data may be indicated to another task schedule for subsequent processing).”
Sanghvi may not explicitly teach of the task schedulers/nodes containing a designated memory address.
Gutierrez teaches polling of memory addresses of predetermined memory locations such that it teaches the limitation “monitoring... designated memory addresses corresponding to at least one first signal... ([0014] teaches that events are associated with completion objects such as signals (e.g. predetermined memory locations), interrupts, or polling of memory addresses such that the signals received by the HSM are from designated memory addresses)”.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of Gutierrez with the invention of Sanghvi to show that signals received may be from predetermined memory locations. A person having ordinary skill in the art would have been motivated to make this combination as it provides a known mechanism for communicating task completion to scheduling hardware through monitored memory locations. Together, Gutierrez in combination with Sanghvi teach every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
Regarding claim 5, the combination teaches “The method of claim 1, wherein notifying the another processing unit comprises: notifying the another processing unit of a first completed task by the first processing unit and a second completed task by the at least one second processing unit (Sanghvi [0044-0049] teaches a tdone signal and pend signal such indicating task completion to other task schedulers).”
Regarding claim 6, the combination teaches “The method of claim 1, wherein notifying the another processing unit comprises: delivering a first interrupt code to a memory-mapped input/output (MMIO) port of the another processing unit; and delivering a second interrupt code to the MMIO port of the another processing unit (Sanghvi [0026] teaches that task schedulers are connected to a scheduler crossbar that may be configured by memory mapped registers, allowing task schedulers to communicate between each other and deliver interrupts as seen in Sanghvi [0034-0035]).”
13. Regarding claim 7, wherein the combination, Sanghvi teaches “The method of claim 6, wherein the first interrupt code corresponds to the first stored value and the second interrupt code corresponds to the second stored value ([0034] teaches of a pend interrupt which may correspond to a pend signal [0030], and that each task scheduler is able to signal a pend signal which may trigger the corresponding pend interrupt).”
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Sanghvi and Gutierrez as used in claim 1, and in further view of Fu et al. Pub. No. US 2017/0168895 A1 (hereafter Fu).
Regarding claim 2, the combination may teach of task identifiers (Gutierrez [0037]) and queueing tasks in response to detecting the completion of objects (Gutierrez [0021]) but may not explicitly teach enqueueing a completed task ID to a completion queue.
Fu teaches queuing task-ID of a completed task such that it teaches the limitation “The method of claim 1, wherein notifying the another processing unit comprises: enqueuing a first task identification (ID) into a completion queue of the another processing unit; and enqueuing a second task ID into the completion queue of the another processing unit. ([0046-0047] teach that for any completed task, a decoder done control block may output the task-ID of a completed task to a done status queue)”.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of Fu with the combination of Sanghvi and Gutierrez to show completed tasks may enqueue task IDs into queues indicating completion. A person having ordinary skill in the art would have been motivated to make this combination as it may maximize overall throughput (Fu [0035]).
9. Regarding claim 3, the combination teaches “The method of claim 2, wherein the first task ID indicates completion of a first task by the first processing unit and the second task ID indicates completion of a second task by the second processing unit. (Sanghvi [0046] teaches a task scheduler signaling tdone and pend indicating that task is complete and data is available; Sanghvi [0050] teaches that a task may correspond to the task scheduler Fu [0045] teaches the task-ID may be used to identify a block that owned the task such that when combined, task-ID may indicate completion corresponding to a task scheduler).”
10. Regarding claim 4, the combination teaches “The method of claim 2, wherein the first task ID indicates an origin of the at least one first signal and the second task ID indicates an origin of the at least one second signal (Fu [0045] teaches the task-ID identifying a control block that owned the task, such that when combined with Sanghvi [0050], a task corresponding to a task scheduler may indicate the origin (task scheduler) to the signal produced).”
Claims 8-13 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Sanghvi and Gutierrez as used in claim 1, and in further view of UGALE et al. Pub. No. US 2021/0109759 A1 (hereafter UGALE).
14. Regarding claim 8, the combination teaches “A method, comprising: monitoring, at a first hardware signal monitor (HSM), designated memory addresses corresponding to a first signal from a first processing unit; receiving, at the first HSM, a first stored value in the first signal from the first processing unit that has completed a first task ... (Sanghvi [0030-0033], [0044-0049], & Gutierrez [0014]).
The combination may not explicitly teach of a callback.
UGALE teaches a callback pointer such that it teaches the limitation “… and executing a callback, by the first HSM, based on the first stored value in the first signal ([0011-0012] teaches calling a callback pointer for the compression job to notify when the accelerator is ready).”
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of UGALE with the combination of Sanghvi and Gutierrez to implement a callback routine for accelerators. A person having ordinary skill in the art would have been motivated to make this combination to improve the efficiency of data processing, possibly reducing load and network bandwidth in a data processing system (UGALE [0016-0018]). Together, UGALE in combination with Sanghvi and Gutierrez teach every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
15. Regarding claim 9, the combination teaches “The method of claim 8, further comprising: based on execution of the callback, invoking one of: a second processing unit; and a third processing unit (Sanghvi [0026] teaches a plurality of task schedulers that are connected to a crossbar that may be configured by various memory mapped registers; UGALE Fig. 1, [0022] teach one or more hardware accelerators; such that when calling a callback pointer for notifying that an accelerator is available, it may be a second or third accelerator invoked to carry out the job UGALE [0011-0012]).”
Regarding claim 10, wherein the combination, Sanghvi teaches “The method of claim 9, wherein invoking the second processing unit comprises: one of: sending, by the first HSM, the first task to the second processing unit; and sending, by the first HSM, a second task to the second processing unit, wherein the second task is different from the first task ([0005] teaches that a first thread includes tasks of a first subset of hardware and a second thread includes tasks of a second subset of hardware such that there may be different tasks; [0027] teaches that tasks managed by a task scheduler may be a consumer task or a producer task or both; [0031] teaches connecting signals of the task schedulers for the desired tasks such that each respective scheduler/node may process a different task).”
16. Regarding claim 11, the combination teaches “The method of claim 9, further comprising: monitoring, at a ... HSM, designated memory addresses corresponding to a second signal from one of the second processing unit and the third processing unit; receiving, at the ... HSM, a second stored value in the second signal from one of: the second processing unit; and the third processing unit; and notifying, by the ... HSM, another processing unit that the first task has been completed in response to processing the second signal based on the second stored value (Sanghvi [0030-0033, 0044-0049], Gutierrez [0014]).”
The combination does may not explicitly teach of a second HSM.
Sanghvi [0030-0032] teaches a task scheduler sending a pend signal up to the scheduler crossbar wherein it may indicate that data is available for subsequent processing by another task scheduler, such that it must go through a second instance of the HSM, effectively describing a second HSM.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to derive receiving the completed task and available data the HSM for subsequent processing of the task. One would be motivated by the desire to perform subsequent operations on tasks that have yet to indicate end of processing.
17. Regarding claim 12, wherein the combination, Sanghvi teaches “The method of claim 9, further comprising: monitoring, at a second HSM, designated memory addresses corresponding to a second signal from one of the second processing unit and the third processing unit; and receiving, at the second HSM, a second stored value in the second signal from the second processing unit and a third stored value in a third signal from the third processing unit. ([0030] teach of a plurality of task schedulers connected to the scheduler crossbar by two signals, wherein each task scheduler may indicate a pending signal; [0030] teaches a plurality of signals)”
18. Regarding claim 13, wherein the combination, Gutierrez teaches “The method of claim 8, wherein executing the callback comprises: interpreting the first stored value as a command packet ([0032] teaches that signals may be implemented as Heterogenous System Architecture (HSA) signals or Architected Queuing Language (AQL) as taught in [0002]).”
19. Regarding the system of claim 16, it is similar to claim 8, and is rejected for the same reasons. Claim 16 is directed towards a system (Sanghvi [0020]).
20. Regarding the system of claim 17, it is similar to claim 9, and is rejected for the same reasons.
21. Regarding the system of claim 18. It is similar to claim 11, and is rejected for the same reasons.
22. Claims 14, 15, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sanghvi, Gutierrez, and UGALE as applied in claims 8 and 16, and in further view of Chew Pub. No. 2017/0329729 A1.
23. Regarding claim 14, the combination may not explicitly teach that when executing a callback, it executes a function.
Chew teaches a pointer to a callback function such that it teaches the limitation “The method of claim 8, wherein executing the callback comprises: executing a function pointer by directing the first HSM to execute a function at a location defined in the first stored value. ([0181-0183] teaches, in response to a completed task, invoking a corresponding callback function pointer back to a memory address such that it represents the location of the stored value).”
It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of Chew with the combination of Sanghvi, Gutierrez, and UGALE to implement a callback pointer function. A person having ordinary skill in the art would have been motivated to make this combination to allow for streamlined responses upon the completion of a task. Together, Chew in combination with Sanghvi, Gutierrez, and UGALE, teach every limitation of the claimed invention. Since the teachings were analogous art known at the filing time of the invention, one of ordinary skill could have applied said teachings to achieve expected results.
24. Regarding claim 15, wherein the combination, Chew teaches “The method of claim 8, wherein executing the callback is based on a table of functions stored by the first HSM ([0153] teaches a registry table that keeps track of each thread ID and callback function pointers associated with each task).”
25. Regarding the system of claim 19, it is similar to claim 14, and is rejected for the same reasons.
26. Regarding the system of claim 20, it is similar to claim 15, and is rejected for the same reasons.
References not cited but are pertinent to the art are as follows:
US 20220308879 A1
teaches
Accelerator Interface Mechanism For Data Processing System
US 20200019451 A1
teaches
HELPING A HARDWARE ACCELERATOR USING SOFTWARE
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRANDON NGUYEN/Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
