Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 16, 19-22, 24 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang et al. (US 20230402316 A1) hereafter referred to as Wang
In regard to claim 1 Wang teaches a semiconductor device [see Fig. 1 see paragraph 0020] comprising:
a semiconductor layer [“the first substrate 110 is a silicon substrate”], in which a semiconductor element [“Various CMOS devices are formed in the chip region of the first wafer 100. Each CMOS device includes, but is not limited to, a transistor and a photodiode” “when the CMOS image sensor chip in the first wafer 100 is a photon time of flight (TOF) CMOS image sensor chip” “the semiconductor structure further includes a first electro-static discharge (ESD) protection module 300, arranged in the first substrate 110” ] is arranged, and which forms a part of a first surface [top of 110] and a part of a second surface [bottom of 110];
a wiring structure, which is arranged so as to cover the second surface, and includes, in an insulator [“first dielectric layer 120”], wiring layers [“first interconnecting structure 121” “interconnecting structure 4051”] each including a wiring pattern extending in a direction along the second surface; and
a pad [“pad structure 112”] for external connection, wherein an opening portion [“pad groove 111 is configured for the pad structure 112 to be formed therein”] for exposing the pad is provided in the first surface,
the pad is arranged between the first surface and a wiring layer [see Fig. 1 see 121 is below 112] closest to the second surface among the wiring layers arranged in the wiring structure, and has a third surface [top of 112] which partially exposed by the opening portion,
an insulating portion [“a material of the passivation layer 114 is silicon nitride (SiN). In other forms, the material of the passivation layer 114 may further be at least one of silicon oxide (SiO2), silicon carbide (SiC), or a high-k dielectric material”] forming a part of the second surface [see 114 touches 120] is embedded in the semiconductor layer, a portion of the insulating portion forming the second surface is in contact [see 114 touches 120] with the insulator, in an orthogonal projection with respect to the first surface, an outer edge [see Fig. 1 “passivation layer 114 is configured to achieve isolation between the sidewall of the pad groove 111 and the pad structure 112”] of the insulating portion is arranged so as to surround an outer edge of the pad, and
a wall surface of the opening portion is formed by [see Fig. 1 “passivation layer 114” is on the wall of the opening] the semiconductor layer and the insulating portion, or formed by the insulating portion.
In regard to claim 3 Wang teaches wherein the third surface is arranged between [see Fig. 1] the first surface and the second surface.
In regard to claim 4 Wang teaches wherein a part of the third surface is in [see Fig. 1] contact with the insulating portion.
In regard to claim 6 Wang teaches wherein a side surface of the pad [see Fig. 1, see Fig. 8 the side of the pad is not a straight line because see Fig. 7 the trench in 120 to reach the uppermost line “first interconnecting structure 121 includes a first interconnecting layer structure (not shown) composed of a plurality of metal interconnecting lines and a first via structure (not shown) configured to connect the metal interconnecting lines” see the side of the pad structure 112 touches 114 and also 120 and see the bottom side of the pad as shown in Fig. 1, Fig. 8 is “fourth” surface and is touching the uppermost line ] connecting the third surface and a fourth surface on the opposite side of the third surface is in contact with the insulating portion and the wiring structure.
In regard to claim 7 Wang teaches wherein in the orthogonal projection with respect to the first surface, the wall surface is arranged [see Fig. 1 the wall surface is outside the pad, and this is seen in the orthogonal projection with respect to the first surface, see “passivation layer 114 is configured to achieve isolation between the sidewall of the pad groove 111 and the pad structure 112”] so as to surround the outer edge of the pad.
In regard to claim 9 Wang teaches wherein in the orthogonal projection with respect to the first surface, the outer edge [see Fig. 1 see that 114 is on the side of the wall and then extends out of the opening onto the top of 110 around the opening ] of the insulating portion is arranged so as to surround the wall surface.
In regard to claim 10 Wang teaches wherein the opening portion includes a first portion [see Fig. 1 this is the upper portion of 114 above the level of the pad top surface], and a second portion arranged between [see Fig. 1 this is the lower portion of 114 below the level of the pad top surface] the first portion and the pad, and in the orthogonal projection with respect to the first surface, a wall surface of the first portion of the wall surface is arranged so as to surround [see Fig. 1 this is because the sidewall of the opening is tapered so the lower part has a smaller diameter than the upper part] the outer edge of the insulating portion, and a wall surface of the second portion of the wall surface is arranged between [see Fig. 1 this is the lower portion of 114 below the level of the pad top surface] the outer edge of the insulating portion and the outer edge of the pad.
In regard to claim 12 Wang teaches wherein the pad is in contact with [see Fig. 7, Fig. 8 “the step of forming the pad groove 111 includes: forming a patterned third mask layer on the surface of the first substrate 110 facing away from the first dielectric layer 120; etching the first substrate 110 by using the third mask layer as a mask, to form a first interconnecting trench extending through the first substrate 110 along the direction from the first substrate 110 to the first dielectric layer 120; and etching the first dielectric layer 120 on a bottom of the first interconnecting trench to the partial thickness after the first interconnecting trench is formed, to form the first interconnecting via”, compare to instant Application Fig. 2 see the “conductive pattern 106” corresponds to the uppermost via of the Wang Fig. 8, see in instant Application Fig. 2 the 103 touches 111a, similarly in Wang Fig. 8 “the pad structure 112 includes a pad via (not shown) and a metal pad layer (not shown) above the pad via” thus the pad touches the uppermost line, see the shape is the opening in Fig. 7, see the width of the opening in 120 is wider than the vias on the left and right, the Examiner notes that any perceived difference between the instant Application and Wang is basically in nomenclature, under broadest reasonable interpreation, it is only the structure that shows the limitation ] a wiring pattern arranged in a wiring layer closest [i.e. the uppermost line “first interconnecting structure 121 includes a first interconnecting layer structure (not shown) composed of a plurality of metal interconnecting lines and a first via structure (not shown) configured to connect the metal interconnecting lines”] to the second surface among the wiring layers arranged in the wiring structure.
In regard to claim 13 Wang teaches wherein the pad is connected, via [see Fig. 7, Fig. 8 “the step of forming the pad groove 111 includes: forming a patterned third mask layer on the surface of the first substrate 110 facing away from the first dielectric layer 120; etching the first substrate 110 by using the third mask layer as a mask, to form a first interconnecting trench extending through the first substrate 110 along the direction from the first substrate 110 to the first dielectric layer 120; and etching the first dielectric layer 120 on a bottom of the first interconnecting trench to the partial thickness after the first interconnecting trench is formed, to form the first interconnecting via”, compare to instant Application Fig. 2 see the “conductive pattern 106” corresponds to the uppermost via of the Wang Fig. 8, see in instant Application Fig. 2 the 103 touches 111a, similarly in Wang Fig. 8 “the pad structure 112 includes a pad via (not shown) and a metal pad layer (not shown) above the pad via” “In other forms, the pad structure 112 may further include a plurality of metal pad layers and a plurality of pad vias used for interconnecting the metal pad layers” i.e. the “via” is the “conductive member” , the Examiner notes that any perceived difference between the instant Application and Wang is basically in nomenclature, under broadest reasonable interpreation, it is only the structure that shows the limitation] a conductive member, to a wiring pattern arranged in a wiring layer closest [i.e. the uppermost line “first interconnecting structure 121 includes a first interconnecting layer structure (not shown) composed of a plurality of metal interconnecting lines and a first via structure (not shown) configured to connect the metal interconnecting lines”] to the second surface among the wiring layers arranged in the wiring structure.
In regard to claim 15 Wang teaches wherein the wiring structure includes a semiconductor layer [“the semiconductor structure further includes a second wafer 200 bonded to the first wafer 100” “second wafer 200 has a plurality of signal processing chips”] different from the semiconductor layer.
In regard to claim 16 Wang teaches wherein an element configured to operate the semiconductor element is [see “when the CMOS image sensor chip in the first wafer 100 is a photon time of flight (TOF) CMOS image sensor chip” “In this form, the second wafer 200 is a signal processing (Digital Signal Processor, DSP) wafer. Specifically, the second wafer 200 has a plurality of signal processing chips. A logic circuit for signal control, reading, and processing is formed in each signal processing chip, and the signal processing chip is configured to process an electrical signal converted from a light signal” “In this form, the semiconductor structure is a 3D stacked BSI CMOS image sensor”] arranged in the different semiconductor layer.
In regard to claim 19 Wang teaches wherein the semiconductor layer comprises [“the first wafer 100 is a photosensitive wafer. Specifically, the first wafer 100 has a plurality of image sensor chips. The image sensor chip is configured to receive a light signal and convert the light signal to an electrical signal. The image sensor chip is correspondingly a CMOS image sensor chip” “The first region I is a portion of a chip region of the first wafer 100. A CMOS device is formed in the chip region of the first wafer 100. The CMOS device includes, but is not limited to, a transistor and a photodiode”] a pixel region in which a pixel including the semiconductor element is arranged.
In regard to claim 20 Wang teaches wherein the wiring structure further includes a conductive member configured to electrically connect [see Fig. 1 see the vias on the left side and right side connecting to semiconductor 110 “first interconnecting structure 121 includes a first interconnecting layer structure (not shown) composed of a plurality of metal interconnecting lines and a first via structure (not shown) configured to connect the metal interconnecting lines”] the semiconductor layer and a wiring pattern arranged in a wiring layer closest to the second surface among the wiring layers arranged in the wiring structure.
In regard to claim 21 Wang teaches further including a substrate [see Fig. 1 see “the semiconductor structure further includes a second wafer 200 bonded to the first wafer 100”] stacked on the semiconductor layer via the wiring structure.
In regard to claim 22 Wang teaches wherein an element configured to operate [see “when the CMOS image sensor chip in the first wafer 100 is a photon time of flight (TOF) CMOS image sensor chip” “In this form, the second wafer 200 is a signal processing (Digital Signal Processor, DSP) wafer. Specifically, the second wafer 200 has a plurality of signal processing chips. A logic circuit for signal control, reading, and processing is formed in each signal processing chip, and the signal processing chip is configured to process an electrical signal converted from a light signal”] the semiconductor element is arranged in the substrate.
In regard to claim 24 Wang teaches an apparatus comprising: the semiconductor device according to claim 1; and [see “when the CMOS image sensor chip in the first wafer 100 is a photon time of flight (TOF) CMOS image sensor chip” “In this form, the second wafer 200 is a signal processing (Digital Signal Processor, DSP) wafer. Specifically, the second wafer 200 has a plurality of signal processing chips. A logic circuit for signal control, reading, and processing is formed in each signal processing chip, and the signal processing chip is configured to process an electrical signal converted from a light signal” “In this form, the semiconductor structure is a 3D stacked BSI CMOS image sensor”] a processing device configured to process a signal output from the semiconductor device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 5, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20230402316 A1) hereafter referred to as Wang in view of Qian et al. (US 20220165670 A1) hereafter referred to as Qian
In regard to claim 2 Wang does not teach wherein the opening portion is not arranged in the wiring structure.
See Qian Fig. 2, Fig. 5 “FIG. 2 is a schematic cross-sectional view of a semiconductor device of FIG. 1 that includes an image sensor, according to an embodiment” “metal interconnection structure 222 is electrically connected to the metal pad 210 by a set of conductive contacts 224” “Above the inter-layer dielectric layer 204 is a low-κ dielectric layer (low-κ inter-layer dielectric layer) 220 into which a metal interconnection structure 222 is embedded”, see that the pad 210 is formed in a recess in the “semiconductor substrate 202” but does not enter the (low-κ inter-layer dielectric layer) 220.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Wang to include wherein the opening portion is not arranged in the wiring structure.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is ease of manufacture by using an equivalent structure by using vias formed in interconnecting structure 121 to the surface of 120 to connect to pad 112 of Wang.
In regard to claim 5 Wang does not teach wherein in the orthogonal projection with respect to the first surface, the outer edge of the pad is arranged so as to surround the wall surface.
See Qian Fig. 2, Fig. 5 the opening to expose the pad 110 is smaller than the pad 110 see “insulating liner layer 517” “conductive layer 514”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Wang to include wherein in the orthogonal projection with respect to the first surface, the outer edge of the pad is arranged so as to surround the wall surface.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is space saving and better structural integrity by making smaller holes.
In regard to claim 14 Wang does not teach wherein the insulating portion comprises an STI structure.
See Qian Fig. 2, Fig. 5 see Block 420 “Using block 420 of method 400, a recess-insulating layer 503 is deposited that coats a semiconductor substrate surface 515 that forms the recess 516. In one example, the thickness of recess-insulating layer 503 may be configured to define a size of the metal pad” see Block 470 where the pad is exposed from the other side.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Wang to include wherein the insulating portion comprises an STI structure.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that placing the pad in the STI, then making the opening to expose pad gives good structural strength and good electrical contact with ease of manufacture.
Claim(s) 8, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20230402316 A1) hereafter referred to as Wang in view of Kagawa et al. (US 20160233264 A1) hereafter referred to as Kagawa
In regard to claim 8 Wang does not teach wherein a part of a side surface of the pad connecting the third surface and a fourth surface on the opposite side of the third surface is exposed to the opening portion, and a remaining part of the side surface is in contact with the wiring structure.
See Kagawa Fig. 11 see paragraph 0158 “a pad 111 for wire bonding and a contact 112-1 to a contact 112-5 that are formed of tungsten (W) are provided in a wiring layer L31 which is provided adjacent to the Si substrate 31 in the wiring layer 32 constituted by a plurality of wiring layers”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Wang to include wherein a part of a side surface of the pad connecting the third surface and a fourth surface on the opposite side of the third surface is exposed to the opening portion, and a remaining part of the side surface is in contact with the wiring structure.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is ease of manufacture by allowing the entire surface to be available for wire bonding.
In regard to claim 11 Wang does not teach wherein a part of a side surface of the pad connecting the third surface and a fourth surface on the opposite side of the third surface is exposed to the opening portion, and a remaining part of the side surface is in contact with the insulating portion and the wiring structure.
See Kagawa Fig. 11 see paragraph 0158 “a pad 111 for wire bonding and a contact 112-1 to a contact 112-5 that are formed of tungsten (W) are provided in a wiring layer L31 which is provided adjacent to the Si substrate 31 in the wiring layer 32 constituted by a plurality of wiring layers”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Wang to include wherein a part of a side surface of the pad connecting the third surface and a fourth surface on the opposite side of the third surface is exposed to the opening portion, and a remaining part of the side surface is in contact with the insulating portion and the wiring structure.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is ease of manufacture by allowing the entire surface to be available for wire bonding.
Claim(s) 17, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20230402316 A1) hereafter referred to as Wang in view of Mase (US 20230283866 A1)
In regard to claim 17 Wang does not teach further including a semiconductor layer different from the semiconductor layer so as to cover the first surface.
See Mase Fig. 1 the “second pixel portion 23 includes a plurality of second pixels 25” “second semiconductor layer 21 includes a second pixel portion 23” are under “first semiconductor layer 11 includes a first pixel portion 13” see sensitivity is for L1 and L2.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Wang to include further including a semiconductor layer different from the semiconductor layer so as to cover the first surface.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to increase the range of detection.
In regard to claim 18 Wang and Mase as combined teaches [see two pixel portions in two layers are used for imaging and are controlled just like the imaging of Wang] wherein the different semiconductor layer comprises a pixel region in which a pixel operated by the semiconductor element is arranged.
Conclusion
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893