DETAILED ACTION Claims 1-18 are presented for examination. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f): (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: “a generation unit generating a recognizable task…,” “a split unit splitting the task…,” “an allocation unit assigning the split tasks….,” and “a concatenation unit concatenating LDPC encoded split tasks…” in claim 1 0 . Because these claim limitations are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to avoid them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid /them being interpreted under 35 U.S.C. 112(f). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim s 1 -3, 5-7, 10-12, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al ( U.S. Pat. No. 8654880 B2, hereinafter Zhou ) in view of Kalachev et al ( U.S. Pat. Pub. No. 2018/0337691 A1, hereinafter Kalachev ) . Zhou was cited in the IDS filed on 12/20/2023. As per claim 1 , Zhou teaches the limitations substantially as claimed, including a method for Low Density Parity Check (LDPC) encoding and decoding for a general-purpose processor in methods for performing LDPC encoding and decoding by a multi-core based general-purpose processor, the method comprising: generating a recognizable task from a plurality of code blocks (CBs) by the general-purpose processor (Figure 1, Element 100, “Transport Stream Input; Figure 7, “Input Signal”; Col. 1, Lines 57-67, OFDM transmission system, high-rate data stream); splitting the task into two or more split tasks (Col. 15, Lines 50-51, “de-maps the symbols into three sets of bitstreams”) ; assigning the split tasks into the respective cores (Col. 15, Lines 59-61) ; generating LDPC encoded split tasks by performing LDPC encoding and/or LDPC decoding on each code block within the split task of the core (Col. 16, Lines 4-15) ; and concatenating the LDPC encoded split tasks (Col. 16, Lines 23-28) . Zhou does not expressly teach that the respective paths are cores. However, Kalachev teaches that the respective paths are cores (Paragraph [0046]). It would have been obvious to one of ordinary skill in the art at the time of the filing of the application to combine the teachings of Kalachev with those of Zhou in order to allow for Zhou’s method to take advantage of multicore technologies, which can allow for faster processing of heavier workloads, potentially leading to greater buy-in among prospective users. As per claim 2 , Zhou teaches setting the number of cores to perform LDPC encoding and/or LDPC decoding among the multi-cores (Col. 7, Lines 42-47) . As per claim 3 , Zhou teaches that the setting of the number of cores isolates one or more specific cores from the multi-cores and sets the number of isolated cores to the number of cores (Col. 7, Lines 42-47). As per claim 5 , Zhou teaches that the maximum value of the number of split tasks is predetermined according to the data processing capacity of the general-purpose processor (Col. 7, Lines 42-47). As per claim 6 , Zhou teaches that the number of split tasks is set to the minimum value among the maximum value of the number of split tasks, the number of code blocks, and the number of cores (Col. 15, Lines 50-51). As per claim 7 , Zhou teaches that the number of code blocks included in the split task corresponds to the total number of code blocks divided evenly by the number of cores (Col. 15, Lines 50-51) . As per claims 10-12 and 14-16 , they are device claims with no further limitations beyond those rejected above. Therefore, they are rejected for the same reasons. Claims 4, 8, 9, 13, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou and Kalachev , as applied to claim 2 above, and further in view of Sorenson, III et al ( U.S. Pat. Pub. No. 2014/0310418 A1, hereinafter Sorenson ) . As per claim 4 , Zhou and Kalachev do not expressly teach that the setting of the number of cores sets the number of cores with a utilization rate of less than or equal to a predetermined value among the multi-cores to the number of cores. However, Sorenson teaches that the setting of the number of cores sets the number of cores with a utilization rate of less than or equal to a predetermined value among the multi-cores to the number of cores (Paragraph [0063]). It would have been obvious to one of ordinary skill in the art at the time of the filing of the application to combine the teachings of Sorenson with those of Zhou and Kalachev in order to allow for Zhou’s and Kalachev’s method to more efficiently utilize available hardware, potentially leading to faster and more efficient processing and thus greater buy-in among prospective users. As per claim 8 , Sorenson teaches that t he number of code blocks included in the split task has a different value depending on the utilization rate of the core allocated to the split task (Paragraph [0063]) . As per claim 9 , Sorenson teaches that the utilization rate of the core and the number of code blocks included in the split task have an inversely proportional relationship (Paragraph [0063]) . As per claims 13, 17, and 18 , they are device claims with no further limitations beyond those rejected above. Therefore, they are rejected for the same reasons. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT Gregory Kessler whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7762 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-Th 8:30 - 5, Alternate Fridays 8:30-4 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Bradley Teets can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)272-3338 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GREGORY A KESSLER/ Primary Examiner, Art Unit 2197