Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s filing of claims 1-15 on 12/20/23 is acknowledged. Claims 1-15 are pending and are under examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/16/24 was acknowledged. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 7 are rejected because “the fluidic channel” raises an antecedent basis issue.
Claim 7 is rejected because “the structure” raises an antecedent basis issue.
Claim 7 is rejected because “the electrode” raises an antecedent basis issue.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuo et al. (“Kuo,” US 9670445, cited in IDS).
As to claim 1, Kuo discloses a microfluidic device (200) comprising: at least one structure arranged in a pocket-defining layer (542) defining a pocket in the pocket-defining layer; a semiconductor chip (204) arranged in the pocket, the semiconductor chip comprising at least one electrode (206 and/or 212) at the surface of the semiconductor chip; an electrical connection layer (214) arranged above the semiconductor chip, wherein the electrical connection layer comprises electronic connections (428 and/or 440) electrically connected to the at least one electrode and arranged to extend laterally in the electrical connection layer away from the semiconductor chip; at least one fluidic channel (762, 864 and/or 866) extending through the pocket-defining layer and above the semiconductor chip, the fluidic channel being arranged to be in fluidic communication with the at least one electrode (e.g., col. 2-7 et seq.).
As to claim 2, Kuo discloses the electronic connections of the electrical connection layer extend along a first direction from the semiconductor chip and the at least one fluidic channel extends through the electrical connection layer at a position separated from the semiconductor chip along a second direction different from the first direction (e.g., col. 3-6 et seq.).
As to claim 3, Kuo discloses the device further comprises a fluidic cartridge arranged below the pocket-defining layer, wherein the at least one fluidic channel extends from the fluidic cartridge through the pocket defining layer and above the semiconductor chip (e.g., fig. 9, col. 6 et seq.).
As to claim 4, Kuo discloses the microfluidic device further comprises a support structure (652) arranged to fill a spacing between walls of the pocket and the semiconductor chip (e.g., col. 5 et seq.).
As to claim 5, Kuo discloses the at least one fluidic channel comprises a transparent layer (754) arranged above and spaced from the semiconductor chip (e.g., col. 2 et seq.).
As to claim 6, Kuo discloses the microfluidic device further comprises a passivation layer arranged above the electrical connection layer (e.g., col. 6 et seq.).
As to claim 7, Kuo teaches a method for manufacturing a microfluidic device, the method comprising: a) forming a pocket by at least one structure arranged on a temporary carrier, wherein the structure is arranged in a pocket-defining layer; b) arranging a semiconductor chip in the pocket, the semiconductor chip comprising at least one electrode at a surface of the semiconductor chip, wherein the semiconductor chip is placed with the electrode facing the temporary carrier; c) arranging a substrate above the at least one structure and the semiconductor chip, wherein the at least one structure and the semiconductor chip is bonded to an upper plane of the substrate; d) removing the temporary carrier such that the surface of the semiconductor chip having the electrode is exposed; e) electrically connecting the surface of the at least one electrode to electronic connections, wherein the electronic connections are arranged in an electrical connection layer and arranged to extend laterally in the electrical connection layer away from the semiconductor chip; f) forming at least one fluidic channel through the pocket-defining layer and above the semiconductor chip, the fluidic channel being arranged to be in fluidic communication with the at least one electrode (see above, fig. 1 and col. 2 et seq.).
As to claim 8, Kuo teaches the method further comprises removing the substrate (e.g., col. 3 et seq.).
As to claim 9, Kuo teaches the method further comprises g) arranging a fluidic cartridge below the pocket-defining layer, such that the at least one fluidic channel is extending from the fluidic cartridge and through the pocket-defining layer (e.g., col. 2-7 et seq.).
As to claim 10, Kuo teaches the method further comprises, after b) and before c), b) i) filling spacings between the semiconductor chip and walls of the pocket with a support structure (e.g., col. 2-7 et seq.).
As to claim 11, Kuo teaches during e) the electronic connections of the electrical connection layer are arranged to extend along a first direction from the semiconductor chip and wherein during f) the at least one fluidic channel is arranged to extend through the electrical connection layer at a position separated from the semiconductor chip along a second direction different from the first direction (e.g., col. 2-7 et seq.).
As to claim 12, Kuo teaches the temporary carrier comprises one or more alignment mark to align a position of the pocket with the one or more alignment mark (e.g., col. 11 et seq.).
As to claim 13, Kuo teaches the method is configured to manufacture a plurality of microfluidic devices in parallel (e.g., col. 10 et seq.).
As to claim 14, Kuo teaches the a) forming a pocket by at least one structure arranged on a temporary carrier is made by a mask (e.g., col. 10 et seq.).
As to claim 15, Kuo teaches wherein f) forming of the at least one fluidic channel comprises arranging a transparent layer above and spaced from the semiconductor chip, wherein in case the method is configured to manufacture a plurality of microfluidic devices in parallel the transparent layer is configured to be arranged above the plurality of microfluidic devices (e.g., col. 6 et seq.).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LORE RAMILLANO JARRETT whose telephone number is (571)272-7420. The examiner can normally be reached Monday to Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lyle Alexander can be reached at 571-272-1254.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LORE R JARRETT/Primary Examiner, Art Unit 1797
6/13/2026
Prosecution Insights