Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 12/20/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract of the disclosure is objected to because the abstract contains information already present in the title. Specifically, the abstract states “A method of fabricating a semiconductor device…”. The title states, “Method of fabricating a semiconductor device” and the abstract should be corrected to remove the information already present in the title. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6 – 7, 9, and 18 - 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20150303250 A1 hereinafter Ishikawa.
For claim 1, Ishikawa teaches a method of fabricating a semiconductor device, the method comprising: forming, in a semiconductor substrate (fig. 1B numeral 1), a device isolation trench (fig. 1B numeral 8a, 8b, 8c; fig. 3 numeral 8a, 8b, 8c) that defines active regions (fig. 3 numeral MA1, MA2, MA3, PA1, PA2); forming a first liner dielectric layer that conformally covers a top surface of the semiconductor substrate and an inner wall of the device isolation trench (fig. 4 numeral 6A – 6C); forming, on the semiconductor substrate, a buried dielectric layer that fills the device isolation trench (fig. 6 numeral 7aa; fig. 2B numeral 8a); performing a polishing process on the buried dielectric layer to form a device isolation structure (Par. [0082]); forming on the semiconductor substrate, a mask pattern that runs across the active regions (fig. 3 numeral 2; fig. 8 numeral 2); and using the mask pattern to pattern portions of the active regions and portions of the device isolation structure to form gate trenches (Par. [00 66 - 0067] and Par. [0085 – 0086] teaches using the mask in selective wet etching to form isolation structures 8a – 8C and the cell active areas MA including word lines WL1 and WL2 in the substrate 1 shown in figures 1A – 2C), wherein, after the polishing process, a top surface of the first liner dielectric layer and a top surface of the buried dielectric layer formed by the polishing process are coplanar with each other (fig. 8 shows coplanar top surfaces of the dielectric liner 6A – 6C and the buried dielectric layer 7a – 7c). Ishikawa also teaches an embodiment wherein two dielectric liner layers are present in the isolation trenches and wherein the top surfaces of the first and second dielectric liner layers are coplanar with the buried dielectric layer (fig. 12 numeral 30a – 30c shows a second dielectric liner with the first dielectric liner 6aa, 6ba, and 6ca with coplanar top surfaces with the buried dielectric layer 7a – 7c).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that Ishikawa teaches two dielectric liner layers with coplanar surfaces with a dielectric buried layer after a polishing process, as Ishikawa teaches an embodiment with multiple dielectric liner layers (fig. 12) and that a polishing process can be performed to create coplanar top surfaces of the buried dielectric layer and the dielectric liner layers (Par. [0082]). It would be obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the embodiment with the multiple dielectric layers with coplanar top surfaces embodiment in order to improve the boding effectiveness of the dielectric layers in the isolation trenches and avoiding possible bubble formations during the manufacturing process (Par. [0092 – 0094]).
For claim 6, Ishikawa teaches all of claim 1. Ishikawa also teaches the first liner dielectric layer including silicon oxide (Par. [0052]) and the second liner dielectric layer includes silicon nitride (Claim 12 of Ishikawa; Par. [0091] refers to the second dielectric liner layer as the third isolation film same as claim 12).
For claim 7, Ishikawa teaches all of claim 1. Ishikawa also teaches the polishing process includes a chemical mechanical polishing (CMP) process (Par. [0082]).
For claim 9, Ishikawa teaches all of claim 1. Ishikawa also teaches the gate trenches run in a first direction (fig. 2A shows gate trenches Tr1 and Tr2 comprising word lines WL1 and WL2 running in direction X) across the active regions (fig. 2A numeral MA) on the semiconductor substrate (fig. 2B shows the active regions and gate trenches present on top of a substrate), and wherein a width in a second direction of the gate trenches is uniform along the first direction, the second direction being orthogonal to the first direction (fig. 2A shows the width of the trenches Tr1 and Tr2 being uniform in the second direction Y, second direction Y is shown orthogonal to the first direction X).
For claim 18, Ishikawa teaches a method of fabricating a semiconductor device, the method comprising: forming, in a semiconductor substrate (fig. 1B numeral 1), a device isolation trench (fig. 1B numeral 8a, 8b, 8c; fig. 3 numeral 8a, 8b, 8c) that defines active regions (fig. 3 numeral MA1, MA2, MA3, PA1, PA2); forming a first liner dielectric layer that conformally covers a top surface of the semiconductor substrate and an inner wall of the device isolation trench (fig. 4 numeral 6A – 6C); forming, on the semiconductor substrate, a buried dielectric layer that fills the device isolation trench (fig. 6 numeral 7aa; fig. 2B numeral 8a); performing a polishing process on the buried dielectric layer to form a device isolation structure (Par. [0082]); forming on the semiconductor substrate, a mask pattern that runs across the active regions (fig. 3 numeral 2; fig. 8 numeral 2); and using the mask pattern to pattern portions of the active regions and portions of the device isolation structure to form gate trenches (Par. [00 66 - 0067] and Par. [0085 – 0086] teaches using the mask in selective wet etching to form isolation structures 8a – 8C and the cell active areas MA including word lines WL1 and WL2 in the substrate 1 shown in figures 1A – 2C), wherein, after the polishing process, a top surface of the first liner dielectric layer and a top surface of the buried dielectric layer formed by the polishing process are coplanar with each other (fig. 8 shows coplanar top surfaces of the dielectric liner 6A – 6C and the buried dielectric layer 7a – 7c). Ishikawa also teaches an embodiment wherein two dielectric liner layers are present in the isolation trenches and wherein the top surfaces of the first and second dielectric liner layers are coplanar with the buried dielectric layer (fig. 12 numeral 30a – 30c shows a second dielectric liner with the first dielectric liner 6aa, 6ba, and 6ca with coplanar top surfaces at the same vertical level with each other and with the buried dielectric layer 7a – 7c). The second dielectric liner layer is shown to conformally cover the first dielectric liner layer (fig. 12 numeral 30a – 30c). Ishikawa also teaches the gate trenches run in a first direction (fig. 2A shows gate trenches Tr1 and Tr2 comprising word lines WL1 and WL2 running in direction X) across the active regions (fig. 2A numeral MA) on the semiconductor substrate (fig. 2B shows the active regions and gate trenches present on top of a substrate), and wherein a width in a second direction of the gate trenches is uniform along the first direction, the second direction being orthogonal to the first direction (fig. 2A shows the width of the trenches Tr1 and Tr2 being uniform in the second direction Y, second direction Y is shown orthogonal to the first direction X).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that Ishikawa teaches two dielectric liner layers with coplanar surfaces with a dielectric buried layer after a polishing process, as Ishikawa teaches an embodiment with multiple dielectric liner layers (fig. 12) and that a polishing process can be performed to create coplanar top surfaces of the buried dielectric layer and the dielectric liner layers (Par. [0082]). It would be obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the embodiment with the multiple dielectric layers with coplanar top surfaces embodiment in order to improve the boding effectiveness of the dielectric layers in the isolation trenches and avoiding possible bubble formations during the manufacturing process (Par. [0092 – 0094]).
For claim 19, Ishikawa teaches all of claim 18. Ishikawa also teaches that the top surface of the first liner dielectric layer, the top surface of the second liner dielectric layer, and a top surface of the buried dielectric layer are sustainably flat and coplanar with each other (fig. 12 numeral 6aa, 30a, and 7a show the first and second liner dielectric layers coplanar and flat with the buried dielectric layer).
Claim(s) 2 - 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20150303250 A1 hereinafter Ishikawa in further view of US 20160099155 A1 hereinafter Park.
For claim 2, Ishikawa teaches all of claim 1. Ishikawa also teaches forming a first mask layer on the semiconductor substrate (Ishikawa, fig. 9 numeral 2) and that the mask has a plate shape (fig. 2 shows the mask 2 having a plate shape). Ishikawa is silent regarding forming a second mask layer, and forming a pattern from the first mask layer and the second mask layer. Ishikawa does teach exposing portions of the active regions and the isolation structure using the first mask layer (Par. [0066 - 0067] and Par. [0085 – 0086] teaches using the mask in selective wet etching to form isolation structures 8a – 8C and the cell active areas MA including word lines WL1 and WL2 in the substrate 1 shown in figures 1A – 2C).
Park teaches a method for forming a semiconductor device (Park, fig. 4), the method including forming a first mask layer (fig. 4 numeral HP) and a second mask layer (fig. 4 numeral PP) on a semiconductor substrate (fig. 4 numeral 100). The mask are shown to be used to pattern the semiconductor layers to form trenches (fig. 4 – fig. 5 numeral RR).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the multiple mask layers in Park with the mask etching process in Ishikawa in order to film uniformity and etch selectivity (Park, Par. [0048 – 0049]) and to better control the aspect ratio of the trenches or openings formed using the mask layers (Park, Par. [0041 – 0042]).
For claim 3, Ishikawa and Park teach all of claim 2. Ishikawa teaches the top surface of the mask being substantially flat and above the second dielectric liner layer (Ishikawa, fig. 12 shows the mask having a flat top surface; fig. 3 numeral 2). Park also teaches the first mask and the second mask having flat top surfaces (Park, fig. 4 numeral HP and PP).
Allowable Subject Matter
Claims 11 - 17 are allowable primarily because the references of record, alone or in combination, do not anticipate or render obvious the limitations noted therein. For example, independent claim 11’s “…forming a first mask pattern on the semiconductor substrate and a second mask pattern on the first mask pattern, wherein the same pattern is formed in the first mask pattern as in the second mask pattern; performing a first etching process on the active regions and the device isolation structure by using the second mask pattern; removing the second mask pattern; and perform a second etching process on the active regions and the device isolation structure by using the first mask pattern…”. Ishikawa and Park teach using multiple mask patterns. Ishikawa and Park appear to be silent regarding using the second mask to form a mask pattern onto the first mask, removing the second mask pattern, then using the first mask during a second etching process on the active regions and the device isolation structures. Park appears to use the two mask patterns to etch dielectric layers. Ishikawa does not appear to teach removing a second mask layer before etching the active regions and the isolation structures.
Claims 12 – 17 are allowable as primarily being dependent on an allowable base claim.
Any comments considered necessary by applicant MUST be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”
Claims 4 - 5, 8, 10, and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For claim 4, Ishikawa and Park do not appear to teach using the second mask to form a pattern on the active region and the device isolation structure, removing the second mask, then performing a second etching process on the active region and the device isolation structure using the first mask pattern which the pattern from the second mask is formed.
For claim 5, Ishikawa and Park do not appear to teach a first distance between a bottom surface of the semiconductor substrate and the top surface of the first liner dielectric layer is substantially the same as a second distance between the bottom surface of the semiconductor substrate and the top surface of the second liner dielectric layer and a third distance between the bottom surface of the semiconductor substrate and the top surface of the buried dielectric layer. Ishikawa appears to have the second dielectric liner layer having a top surface at a greater distance from the bottom surface of the semiconductor substrate than the top surface of the first dielectric liner layer.
For claim 8 and claim 20, Ishikawa and Park are silent regarding the polishing process including a slurry with an etch selectivity selected with respect to the first liner dielectric layer and the second liner dielectric layer.
For claim 10, Ishikawa and Park are silent forming impurity regions in the active regions on opposite sides of each of the word-line structures. Ishikawa does not explicitly state that impurity regions are formed on opposite sides of the word-line structures. Ishikawa and Park do not appear to teach the formation of impurity structures.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20200013631 A1 teaches using multiple hard masks to form semiconductor trenches in semiconductor materials. It does not appear to teach the creation of impurity regions or multiple dielectric liner layers.
US 20160172488 A1 teaches multiple dielectric layers used in device isolation trenches. It does not appear to teach the use of multiple hard mask patterns.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB T NELSON whose telephone number is (571)272-1031. The examiner can normally be reached Monday through Friday 9:00 AM to 5:00 PM.
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/J.T.N./Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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